target/riscv: rvv-1.0: integer comparison instructions
commit063f8bbca05d859461809c68319517fe711e7bd8
authorFrank Chang <frank.chang@sifive.com>
Fri, 10 Dec 2021 07:56:33 +0000 (10 15:56 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Dec 2021 04:51:36 +0000 (20 14:51 +1000)
treed36ae1e2ef35957121281e3ce99d1cd4f8abb6ce
parentd6be7a35041b010f3bb01197bd7ff06258f70a7f
target/riscv: rvv-1.0: integer comparison instructions

* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
  for either VTA to have undisturbed or agnostic setting.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-48-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvv.c.inc
target/riscv/vector_helper.c