| commit | a75ae09f2a7ed09c017f22f04bf71bd7b453fef7 | |
| author | Frank Chang <frank.chang@sifive.com> | |
| Fri, 10 Dec 2021 07:56:28 +0000 (10 15:56 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Mon, 20 Dec 2021 04:51:36 +0000 (20 14:51 +1000) | ||
| tree | 5d6b9bfd7d1b8bfe6ffd4e6c11b6a6bdfcbca384 | treesnapshot (tar.gz zip) |
| parent | 8b99a110f7ff2c7e1d1294998226b84176384ef3 | commitdiff |
target/riscv: rvv-1.0: single-width bit shift instructions
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-43-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-43-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/insn_trans/trans_rvv.c.inc | diffblobblamehistory |