target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
commitd6c4d3f2a693f4520ec72b0bd25be6ec03fee13a
authorFrank Chang <frank.chang@sifive.com>
Fri, 10 Dec 2021 07:56:53 +0000 (10 15:56 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Dec 2021 04:53:31 +0000 (20 14:53 +1000)
tree4bade95dfa1972d7c5580ae13f9d140e2977e2be
parentf714361ed79180a9780334cfe1b89b69f6c9bfe9
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid

If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.

Call gen_set_rm() with DYN rounding mode to check and trigger illegal
instruction exception if frm field contains invalid value at run-time
for vector floating-point instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-68-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvv.c.inc