2021-02-21 | BALATON Zoltan | vt82c686: Fix up power management io base and config ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | BALATON Zoltan | vt82c686: Correctly reset all registers to default... Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | BALATON Zoltan | vt82c686: Correct vt82c686-pm I/O size ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | BALATON Zoltan | vt82c686: Make vt82c686-pm an I/O tracing region Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | BALATON Zoltan | vt82c686: Fix SMBus IO base and configuration registers ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | BALATON Zoltan | vt82c686: Reorganise code Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | BALATON Zoltan | vt82c686: Move superio memory region to SuperIOConfig... Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Use GPR move functions in gen_HILO1_tx79() ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210214175912.732946-8-f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210214175912.732946-7-f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Rename 128-bit upper halve GPR registers ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210214175912.732946-6-f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Promote 128-bit multimedia registers as... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210214175912.732946-5-f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Make cpu_HI/LO registers public ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210214175912.732946-4-f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Include missing "tcg/tcg.h" header ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210207232310.2505283-4-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Remove unused 'rw' argument from page_table_wal... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210220202026.2305667-1-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Let CPUMIPSTLBContext::map_address() take... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-14-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Let get_seg*_physical_address() take MMUAccessT... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-13-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Let get_physical_address() take MMUAccessType... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-12-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Let raise_mmu_exception() take MMUAccessType... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-11-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Let cpu_mips_translate_address() take... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-10-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Let do_translate_address() take MMUAccessType... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-9-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Replace magic value by MMU_DATA_LOAD definition ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-7-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Remove unused MMU definitions ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-6-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Remove access_type argument from get_physical_a... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-5-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Remove access_type arg from get_segctl_physical... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-4-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Remove access_type argument from get_seg_physic... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-3-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: Remove access_type argument from map_address... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210128144125.3696119-2-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Philippe Mathieu... | target/mips: fetch code with translator_ld ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210125105818.2707067-1-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Jiaxun Yang | tests/acceptance: Test PMON with Loongson-3A1000 CPU Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Jiaxun Yang | hw/intc/loongson_liointc: Fix per core ISR handling ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Jiaxun Yang | hw/mips/boston: Use bootloader helper to set GCRs Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Jiaxun Yang | hw/mips/boston: Use bl_gen_kernel_jump to generate... Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Jiaxun Yang | hw/mips/fuloong2e: Use bl_gen_kernel_jump to generate... Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Jiaxun Yang | hw/mips: Add a bootloader helper Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-21 | Bin Meng | hw/mips: loongson3: Drop 'struct MemmapEntry' Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-20 | Philippe Mathieu... | MAINTAINERS: Add Bin Meng as co-maintainer for SD/MMC... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210216132841.1121653-1-f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: sdhci: Simplify updating s->prnsts in sdhci_sdma_tran... Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: sd: Bypass the RCA check for CMD13 in SPI mode Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: sd: Skip write protect groups check in CMD24... Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: sd: Skip write protect groups check in sd_erase... Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: sd: Move the sd_block_{read, write} and macros... Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: sd: Fix CMD30 response type Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: sd: Only SDSC cards support CMD28/29/30 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: sd: Fix address check in sd_erase() Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: ssi-sd: Handle the rest commands with R1b response... Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: ssi-sd: Fix STOP_TRANSMISSION (CMD12) response ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: ssi-sd: Fix SEND_IF_COND (CMD8) response Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: ssi-sd: Support multiple block write Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: ssi-sd: Support single block write ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: Introduce receive_ready() callback Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: sd: Allow single/multiple block write for SPI... Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: sd: Remove duplicated codes in single/multiple... Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-02-19 | Bin Meng | hw/sd: ssi-sd: Support multiple block read ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-01-24 | Bin Meng | hw/sd: sd.h: Cosmetic change of using spaces Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-01-24 | Bin Meng | hw/sd: ssi-sd: Use macros for the dummy value and tokens... Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-01-24 | Bin Meng | hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-01-24 | Bin Meng | hw/sd: ssi-sd: Add a state representing Nac Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-01-24 | Bin Meng | hw/sd: ssi-sd: Suffix a data block with CRC16 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-01-24 | Bin Meng | util: Add CRC16 (CCITT) calculation routines Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-01-24 | Bin Meng | hw/sd: sd: Drop sd_crc16() Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-01-24 | Bin Meng | hw/sd: sd: Support CMD59 for SPI mode Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-01-24 | Bin Meng | hw/sd: ssi-sd: Fix incorrect card response sequence Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | docs/system: Remove deprecated 'fulong2e' machine alias ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210106184602.3771551-1-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Remove vendor specific CPU definitions ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210112210152.2072996-4-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Remove CPU_NANOMIPS32 definition ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210112210152.2072996-3-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Remove CPU_R5900 definition ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20210112210152.2072996-2-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Convert Rel6 LL/SC opcodes to decodetree ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208203704.243704-14-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Convert Rel6 LLD/SCD opcodes to decodetree ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208203704.243704-13-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208203704.243704-12-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208203704.243704-11-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208203704.243704-10-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201208203704.243704-9-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Convert Rel6 COP1X opcode to decodetree ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201208203704.243704-8-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Convert Rel6 Special2 opcode to decodetree ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201208203704.243704-7-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Remove now unreachable LSA/DLSA opcodes... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201208203704.243704-6-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Introduce decodetree helpers for Release6... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201215225757.764263-24-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Introduce decodetree helpers for MSA LSA... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201215225757.764263-23-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Extract LSA/DLSA translation generators ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201215225757.764263-22-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Use decode_ase_msa() generated from decodetree ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201215225757.764263-21-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Introduce decode tree bindings for MSA ASE ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201215225757.764263-20-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Pass TCGCond argument to MSA gen_check_zero_ele... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201215225757.764263-25-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Extract MSA translation routines ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201120210844.2625602-5-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Declare gen_msa/_branch() in 'translate.h' ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201215225757.764263-18-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Extract MSA helper definitions ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201120210844.2625602-4-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Extract MSA helpers from op_helper.c ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201123204448.3260804-5-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Move msa_reset() to msa_helper.c ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201215225757.764263-15-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208003702.4088927-10-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Remove CPUMIPSState* argument from gen_msa... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208003702.4088927-9-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Extract msa_translate_init() from mips_tcg_init() ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208003702.4088927-8-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Alias MSA vector registers on FPU scalar... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208003702.4088927-7-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Remove now unused ASE_MSA definition ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208003702.4088927-6-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Simplify MSA TCG logic ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208003702.4088927-5-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208003702.4088927-4-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Simplify msa_reset() ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208003702.4088927-3-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Introduce ase_msa_available() helper ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201208003702.4088927-2-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips/translate: Expose check_mips_64() to 32... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201215225757.764263-3-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips/translate: Extract decode_opc_legacy()... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201215225757.764263-2-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Only build TCG code when CONFIG_TCG is set ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201206233949.3783184-20-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Extract FPU specific definitions to translate.h ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201214183739.500368-16-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Declare generic FPU / Coprocessor functions... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201214183739.500368-15-f4bug@amsat.org> |
commitcommitdifftree |
2021-01-14 | Philippe Mathieu... | target/mips: Replace gen_exception_end(EXCP_RI) by... ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> ...Id: <20201214183739.500368-12-f4bug@amsat.org> |
commitcommitdifftree |
next |