| commit | 6902759965852ae9fc099bb32af8f8dc4a098733 | |
| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | |
| Tue, 12 Jan 2021 01:25:27 +0000 (12 09:25 +0800) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Sun, 21 Feb 2021 17:41:46 +0000 (21 18:41 +0100) | ||
| tree | 84686cad27f5cccb802aa3c51a1f25d0b01c9e11 | treesnapshot (tar.gz zip) |
| parent | 283eae174e4944e4f26160aceeec444a13e52b03 | commitdiff |
hw/intc/loongson_liointc: Fix per core ISR handling
Per core ISR is a set of 32-bit registers spaced by 8 bytes.
This patch fixed calculation of it's size and also added check
of alignment at reading & writing.
Fixes: Coverity CID 1438965 and CID 1438967
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Message-Id: <20210112012527.28927-1-jiaxun.yang@flygoat.com>
[PMD: Added Coverity CID]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Per core ISR is a set of 32-bit registers spaced by 8 bytes.
This patch fixed calculation of it's size and also added check
of alignment at reading & writing.
Fixes: Coverity CID 1438965 and CID 1438967
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Message-Id: <20210112012527.28927-1-jiaxun.yang@flygoat.com>
[PMD: Added Coverity CID]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
| hw/intc/loongson_liointc.c | diffblobblamehistory |