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target/riscv: add a MAINTAINERS entry for XVentanaCondOps
2022-02-16 Philipp Tomsichtarget/riscv: add a MAINTAINERS entry for XVentanaCondOps
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: Add XVentanaCondOps custom extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: iterate over a table of decoders
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: access cfg structure through DisasContext
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Philipp Tomsichtarget/riscv: access configuration through cfg_ptr...
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2022-02-16 Philipp Tomsichtarget/riscv: riscv_tr_init_disas_context: copy pointer...
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2022-02-16 Philipp Tomsichtarget/riscv: refactor (anonymous struct) RISCVCPU...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-02-16 Frédéric Pétrottarget/riscv: correct "code should not be reached"...
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2022-02-16 Petr TesarikAllow setting up to 8 bytes with the generic loader
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2022-02-16 Wilfred Mallawainclude: hw: remove ibex_plic.h
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Relax UXL field for debugging
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Enable uxl field write
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2022-01-21 LIU Zhiweitarget/riscv: Set default XLEN for hypervisor
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust scalar reg in vector with XLEN
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust vector address with mask
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2022-01-21 LIU Zhiweitarget/riscv: Fix check range for first fault only
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Remove VILL field in VTYPE
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust vsetvl according to XLEN
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2022-01-21 LIU Zhiweitarget/riscv: Split out the vill from vtype
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2022-01-21 LIU Zhiweitarget/riscv: Split pm_enabled into mask and base
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Calculate address according to XLEN
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Alloc tcg global for cur_pm[mask|base]
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Create current pm fields in env
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust csr write mask with XLEN
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Relax debug check for pm write
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Use gdb xml according to max mxlen
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Extend pc for runtime pc write
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Ignore the pc bits above XLEN
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Create xl field in env
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Sign extend pc for different XLEN
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Sign extend link reg for jal and jalr
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Don't save pc when exception return
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust pmpcfg access with mxl
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Anup Patelroms/opensbi: Remove ELF images
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Anup Patelhw/riscv: Remove macros for ELF BIOS image names
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Anup Patelhw/riscv: spike: Allow using binary firmware as bios
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Allow Zve32f extension to be...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for narrowing...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for widening...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for single...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for scalar...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for configuration...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Allow Zve64f extension to be...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for narrowing...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for widening...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for single...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for scalar...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for vsmul...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for vmulh...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for load...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for configuration...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f extension into RISC-V
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yanan Wangsoftmmu/device_tree: Remove redundant pointer assignment
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Thomas Huthsoftmmu/device_tree: Silence compiler warning with...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: enable riscv kvm accel
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Support virtual time context synchronization
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Implement virtual time adjusting with...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Add kvm_riscv_get/put_regs_timer
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Add host cpu type
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Handle KVM_EXIT_RISCV_SBI exit
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Support setting external interrupt by KVM
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Support start kernel directly by KVM
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Implement kvm_arch_put_registers
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Implement kvm_arch_get_registers
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Implement function kvm_arch_init_vcpu
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Add target/riscv/kvm.c to place the public...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangupdate-linux-headers: Add asm-riscv/kvm.h
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Wilfred Mallawahw: timer: ibex_timer: update/add reg address
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Wilfred Mallawariscv: opentitan: fixup plic stride len
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Wilfred Mallawahw: timer: ibex_timer: Fixup reading w/o register
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Implement the stval/mtval illegal instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Fixup setting GVA
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Set the opcode in DisasContext
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: actual functions to realize crs 128-bit...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: modification of the trans_csrxx for 128...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: helper functions to wrap calls to 128...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: adding high part of some csrs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit M extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit arithmetic instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit shift instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit U-type instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit bitwise instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: accessors to registers upper part and...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: moving some insns close to similar insns
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: setup everything for rv64 to support...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: array for the 64 upper bits of 128-bit...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: separation of bitwise logic and arithmetic...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: additional macros to check instruction...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrotqemu/int128: addition of div/rem 128-bit operations
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrotexec/memop: Adding signed quad and octo defines
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrotexec/memop: Adding signedness to quad definitions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Philipp Tomsichtarget/riscv: Fix position of 'experimental' comment
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frank Changtarget/riscv: rvv-1.0: Call the correct RVF/RVD check...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frank Changtarget/riscv: rvv-1.0: Call the correct RVF/RVD check...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frank Changtarget/riscv: rvv-1.0: Call the correct RVF/RVD check...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Bin Mengroms/opensbi: Upgrade from v0.9 to v1.0
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/riscv: virt: Allow support for 32 cores
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/riscv: Use error_fatal for SoC realisation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Enable the Hypervisor extension by default
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU