| commit | c7a26fb2f6bafd45b983d81d180f624c0e8c4d2b | |
| author | Frank Chang <frank.chang@sifive.com> | |
| Tue, 18 Jan 2022 01:45:05 +0000 (18 09:45 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 21 Jan 2022 05:52:56 +0000 (21 15:52 +1000) | ||
| tree | 37c67be3240be10137a905a82ae5249044eefac1 | treesnapshot (tar.gz zip) |
| parent | b4a99d40276eb5bdfa849cc04344d9a2c4c820ef | commitdiff |
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/insn_trans/trans_rvv.c.inc | diffblobblamehistory |