target/riscv: Add kvm_riscv_get/put_regs_timer
commit27abe66f31efa8bcd15f0f998db2127b4ffb628a
authorYifei Jiang <jiangyifei@huawei.com>
Wed, 12 Jan 2022 08:13:26 +0000 (12 16:13 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 21 Jan 2022 05:52:56 +0000 (21 15:52 +1000)
treece03dd7ec2f27e92cb2d23cd88c87239de639422
parent10f1ca27e0fe9930d372591cd5f302e7249aa705
target/riscv: Add kvm_riscv_get/put_regs_timer

Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
from KVM.

To set register of RISCV_TIMER_REG(state) will occur a error from KVM
on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
that adaping in QEMU.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-11-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/kvm.c