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hw/riscv: microchip_pfsoc: Support direct kernel boot
2021-05-11
Alistair
Francis
targe
t
/riscv:
F
ix the RV64
H
decode comment
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Al
i
stair
Francis
target/risc
v
: Consolida
t
e RV32/64 16-bit instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Ali
s
tair Francis
target/
r
iscv: Consolidate RV32/64
3
2-b
i
t in
s
t
r
uc
t
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fr
a
ncis
target/riscv: Re
m
ove an u
n
u
s
e
d
CASE_OP_32_64
m
acro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
t
arget/riscv
:
Remove
t
h
e unus
e
d
HSTAT
U
S_W
P
RI macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Ali
s
tair Francis
tar
g
et/risc
v
: Remove
t
he hardcoded SATP_MODE m
a
cro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Al
i
s
t
a
i
r F
r
an
c
is
target/r
i
scv: Remove th
e
h
a
rdcod
e
d MS
T
ATUS_SD macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
targ
e
t/riscv: Re
m
ov
e
the
hardcoded HGATP_MOD
E
macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
F
r
ancis
ta
r
g
et/riscv: Remove the hardcoded
SSTATUS
_
SD macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Ali
s
ta
i
r Francis
target/riscv:
Remove the hardcoded RVXLEN
macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fra
n
ci
s
targ
e
t/riscv: Add ePMP
support
for the Ibex
C
PU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
ista
i
r Francis
target
/
riscv
/
pmp: Remo
v
e outdated
c
omm
e
nt
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Al
i
stair Fra
n
c
i
s
t
a
r
g
et/ri
s
c
v
: Add the ePMP fea
t
ure
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alist
a
ir F
r
ancis
ta
r
get/risc
v
: Fi
x
the
PMP is locked check whe
n
us
i
ng TOR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fr
a
ncis
hw/r
i
scv: E
n
a
b
le VIR
T
I
O
_V
G
A
f
o
r
RIS
C
-V virt
m
a
c
h
ine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair F
r
ancis
hw/opentitan: Update the int
e
rru
p
t layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alis
t
air
F
rancis
M
A
INTAINERS: Update the RISC-V CPU Mainta
i
ne
r
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alis
t
a
i
r Francis
target/r
i
scv:
U
se RIS
C
V
Ex
c
e
p
t
i
on
e
num
f
or
C
S
R acces
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
istair F
r
ancis
target/riscv: Use th
e
R
ISCVExce
p
t
ion enum for C
S
R operatio
n
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
target/riscv: Fi
x
3
2
-bit HS
mo
d
e
a
c
c
e
ss
p
ermissions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
t
a
rget/risc
v
: Use the
R
IS
C
VException enum for
C
S
R
p
r
edicates
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
istai
r
Franci
s
targ
e
t
/
riscv:
Conver
t
the RI
S
C-V e
x
ceptions to an enum
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-03-04
Alistair Franc
i
s
MAINTAINERS: Add a Si
F
ive mac
h
ine section
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-02-13
Alistair Francis
linux
-
user/signal: Decode wait
i
d si_code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-01-16
A
l
istair Francis
riscv
:
P
ass RISCVHartArra
y
State by pointer
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fr
a
n
ci
s
r
iscv/open
t
itan
:
Update
t
he
O
penTi
t
an memory l
a
yout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
s
t
a
i
r Fran
c
i
s
hw/riscv: Use th
e
CPU
to determin
e
if
32-bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair Franci
s
tar
g
et/
r
isc
v
: cpu
:
Set X
L
EN independent
l
y
f
ro
m
target
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fran
c
is
target/riscv: csr: Remove compile
time XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
Fr
a
ncis
tar
g
e
t
/riscv: cpu_
h
elper:
R
em
o
ve compile time XL
E
N
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair F
r
a
n
cis
target/riscv: c
p
u: Remove
compile time XLE
N
checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
stair Francis
target/riscv
:
Spec
i
fy the XLEN for CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
targ
e
t
/
riscv: Ad
d
a
risc
v
_cpu_is
_
3
2
bit()
h
e
lp
e
r function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair Fra
n
cis
target/riscv: fpu_h
e
lper
:
Match f
u
n
ction defs i
n
H
E
LPER
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair
Fran
c
is
hw/ri
s
cv: sifiv
e
_u:
R
emove c
o
mpile time XL
E
N check
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
air Fra
n
cis
hw/riscv
:
spike: Remove compi
l
e
t
ime XLEN check
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
Fra
n
cis
hw/riscv: v
i
rt: Re
m
ove c
o
mp
i
le
t
ime XLEN
c
h
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istai
r
Francis
hw/riscv
:
bo
o
t: Remove co
m
pile
time XLEN
c
h
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alista
i
r F
r
ancis
ri
s
cv: v
i
r
t: Remove target
macro condit
i
onals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
F
r
a
n
cis
ri
s
cv: s
p
i
ke: Remove target ma
c
ro conditionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair
Francis
target/riscv: Add a TYPE_RIS
C
V_CPU_BASE CP
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
Francis
hw/riscv: Expand the is 32-bi
t
check to
s
u
pport more
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
air
Francis
intc/ibex_p
l
ic: Cl
e
ar interr
u
p
ts tha
t
occur
d
u
r
ing
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-17
Alistair Franc
i
s
register: Remove
unn
e
cessary
N
U
L
L check
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair Fr
a
ncis
intc
/
i
b
ex_plic
:
E
nsure
w
e don't
loose interrupts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair
Francis
intc/ibe
x
_
plic: Fix some typos in the comm
e
nts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Fr
a
ncis
h
w/intc/ibex_plic: Clear th
e
claim regis
t
er
when
read
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alista
i
r Franci
s
ta
r
get/riscv: Split
the Hypervi
s
or execute load helpers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
l
istair Fran
c
is
target
/
ri
s
cv
:
Remove t
h
e hyp load a
n
d s
t
ore functi
o
ns
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Franci
s
target/riscv: Remove the HS_TWO_STAGE flag
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alista
i
r Franci
s
target/
r
iscv: Set
the virtualis
e
d MMU mode
w
hen doing
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alis
t
air Francis
target/riscv: Add a vir
t
ualis
e
d MMU Mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
Ali
s
tair Francis
linux-user/sys
c
a
l
l: Fix missing targ
e
t_to_host
_
t
i
me
s
pec64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair
F
ranci
s
hw
/
ris
c
v: Load
the
kernel aft
e
r the firmwar
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
tair Francis
h
w/risc
v
: Add a ri
s
c
v
_is_3
2
_bit
(
)
function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
A
listair
F
rancis
h
w
/riscv: R
e
t
urn
the end a
d
dr
e
ss of the
l
oaded firm
w
are
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
ta
i
r Francis
hw/riscv
:
sifi
v
e_u: Allo
w
specifyi
n
g
t
h
e CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
A
l
is
t
a
ir
F
r
ancis
r
i
scv: Convert
inter
r
upt logs to u
s
e qe
m
u_log_mask()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
Alistair Fran
c
is
c
o
re/register: Specify instance
_
s
ize
in the
T
y
p
eInfo
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alis
t
ai
r
Francis
target/
r
iscv: Support
the Virtua
l
Instruction
faul
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
st
a
ir Francis
target/riscv:
Return t
h
e exception from
inv
a
lid CSR
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
sta
i
r Fr
a
ncis
ta
r
get/riscv:
S
u
p
port the v0
.
6 Hypervisor ex
t
e
ns
i
o
n
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
list
a
i
r Fran
c
is
ta
r
get/
r
iscv: Only support littl
e
endian guests
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istair F
r
ancis
target/riscv: Only sup
p
o
r
t a single V
S
XL length
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
Francis
target/riscv: Update the C
S
Rs to t
h
e v0
.
6 Hyp extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Ali
s
tair
Fran
c
is
tar
g
et/
r
iscv: Up
d
a
t
e
t
h
e Hypervisor trap return/en
t
ry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
stair Fr
a
n
c
is
target/ris
c
v: Fix the inte
r
r
upt cause code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair F
r
a
ncis
tar
g
e
t/riscv: Convert MSTATUS MTL
t
o GVA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alis
t
air Francis
target/riscv: Don't allow gu
e
st to wr
i
te
to htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
ra
n
cis
target/
r
isc
v
: Do two-sta
g
e
l
ook
u
ps on hlv/hlvx/hsv
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Franc
i
s
target/riscv: Allow g
e
nerat
i
ng hlv/hlv
x
/
h
sv instruct
i
ons
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/
r
isc
v
: Allow setting a two-stage
l
oo
k
up in the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alist
a
ir
Francis
hw/intc: ibex_
p
lic:
Honour source prio
r
ities
Signed-off-by:
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<alistair.francis@wdc.com>
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2020-08-22
A
lis
t
a
ir Francis
hw/intc:
i
bex_plic: Don't allow repeat interrupts on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-08-22
Alistair F
r
a
n
c
is
hw/intc: i
b
ex_plic: Update
the pending irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-08-21
Al
i
stair F
r
ancis
hw
/
sd/pl
1
81:
Rep
l
ace
f
printf(st
d
err, "*\n")
w
i
t
h error_report()
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
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2020-07-14
Alistair Francis
hw/char: C
o
n
vert the Ibex UART to use
the
r
e
gist
e
rfie
l
ds API
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-07-14
A
listair Fra
n
cis
hw/char
:
C
o
nve
r
t the Ibex UART to use the qdev Clock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-07-02
Alis
t
air Francis
hw/riscv: Allow 64 bi
t
access
to
SiFive CLINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alistair Franc
i
s
target/riscv: Use a smaller guess size for no-MMU
PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Al
i
st
a
ir Fra
n
cis
r
i
scv/opentita
n
: Connect t
h
e UART device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Ali
s
tair Fr
a
ncis
r
i
scv/opentitan: Connect the PLIC device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Al
i
stai
r
Francis
hw/int
c
: In
i
t
ial c
o
mmit of lowRISC Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alistair Francis
hw/cha
r
:
I
nitial co
m
mit of Ibex UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Ali
s
tair Fran
c
is
riscv/openti
t
an: Fix the
ROM size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alistair Franci
s
target/riscv:
I
m
p
l
ement checks for hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alistair Francis
t
a
r
get/riscv: Move the
hfence instructions t
o
t
he
rvh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Ali
s
tair
Francis
target/risc
v
: Report e
r
r
o
rs validatin
g
2nd-stage
PTEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alista
i
r
Francis
ta
r
get/riscv: Set
access a
s
data_load when validating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Al
i
stair
F
rancis
sifive_e: Support the revB machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alis
t
air
F
r
a
ncis
risc
v
: Initial
commit of OpenTitan mac
h
ine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alista
i
r Francis
ta
r
get/ris
c
v: Add
the low
R
I
S
C Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alis
t
ai
r
F
r
ancis
t
a
r
g
et/ris
c
v
: Don't
s
et PMP featur
e
in
t
he
cpu ini
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alis
t
air Francis
target/r
i
scv:
D
isable the MM
U
co
r
r
ectly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistai
r
Francis
target/
r
iscv: Don't overw
r
ite
t
h
e
reset vector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Ali
s
tair Francis
riscv/boot: Add
a miss
i
ng header i
n
clude
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistai
r
Fra
n
cis
ri
s
cv: sifive_
e
:
M
anu
a
lly define the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Fr
a
ncis
docs: deprecated: Update the -bios docume
n
tation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair
F
ranci
s
target/riscv: Dr
o
p support
f
or ISA spec version 1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Ali
s
tair Francis
t
a
rget/riscv: Remo
v
e the deprecated CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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