2022-01-21 | LIU Zhiwei | target/riscv: Relax UXL field for debugging Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Enable uxl field write Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Set default XLEN for hypervisor Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Adjust scalar reg in vector with XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Adjust vector address with mask Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Fix check range for first fault only Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Remove VILL field in VTYPE Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Adjust vsetvl according to XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Split out the vill from vtype Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Split pm_enabled into mask and base Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Calculate address according to XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Alloc tcg global for cur_pm[mask|base] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Create current pm fields in env Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Adjust csr write mask with XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Relax debug check for pm write Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Use gdb xml according to max mxlen Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Extend pc for runtime pc write Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Ignore the pc bits above XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Create xl field in env Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Sign extend pc for different XLEN Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Sign extend link reg for jal and jalr Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Don't save pc when exception return Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | LIU Zhiwei | target/riscv: Adjust pmpcfg access with mxl Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Anup Patel | roms/opensbi: Remove ELF images Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Anup Patel | hw/riscv: Remove macros for ELF BIOS image names Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Anup Patel | hw/riscv: spike: Allow using binary firmware as bios Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Allow Zve32f extension to be... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f support for narrowing... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f support for widening... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f support for single... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f support for scalar... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f support for configuration... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve32f extension into RISC-V Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Allow Zve64f extension to be... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for narrowing... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for widening... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for single... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for scalar... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for vsmul... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for vmulh... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for load... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f support for configuration... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Frank Chang | target/riscv: rvv-1.0: Add Zve64f extension into RISC-V Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yanan Wang | softmmu/device_tree: Remove redundant pointer assignment Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Thomas Huth | softmmu/device_tree: Silence compiler warning with... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: enable riscv kvm accel Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Support virtual time context synchronization Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Implement virtual time adjusting with... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Add kvm_riscv_get/put_regs_timer Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Add host cpu type Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Handle KVM_EXIT_RISCV_SBI exit Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Support setting external interrupt by KVM Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Support start kernel directly by KVM Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Implement kvm_arch_put_registers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Implement kvm_arch_get_registers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Implement function kvm_arch_init_vcpu Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | target/riscv: Add target/riscv/kvm.c to place the public... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Yifei Jiang | update-linux-headers: Add asm-riscv/kvm.h Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Wilfred Mallawa | hw: timer: ibex_timer: update/add reg address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Wilfred Mallawa | riscv: opentitan: fixup plic stride len Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-21 | Wilfred Mallawa | hw: timer: ibex_timer: Fixup reading w/o register Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | target/riscv: Implement the stval/mtval illegal instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | target/riscv: Fixup setting GVA Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | target/riscv: Set the opcode in DisasContext Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: actual functions to realize crs 128-bit... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: modification of the trans_csrxx for 128... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: helper functions to wrap calls to 128... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: adding high part of some csrs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: support for 128-bit M extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: support for 128-bit arithmetic instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: support for 128-bit shift instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: support for 128-bit U-type instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: support for 128-bit bitwise instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: accessors to registers upper part and... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: moving some insns close to similar insns Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: setup everything for rv64 to support... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: array for the 64 upper bits of 128-bit... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: separation of bitwise logic and arithmetic... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | target/riscv: additional macros to check instruction... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | qemu/int128: addition of div/rem 128-bit operations Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | exec/memop: Adding signed quad and octo defines Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frédéric Pétrot | exec/memop: Adding signedness to quad definitions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Philipp Tomsich | target/riscv: Fix position of 'experimental' comment Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frank Chang | target/riscv: rvv-1.0: Call the correct RVF/RVD check... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frank Chang | target/riscv: rvv-1.0: Call the correct RVF/RVD check... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Frank Chang | target/riscv: rvv-1.0: Call the correct RVF/RVD check... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Bin Meng | roms/opensbi: Upgrade from v0.9 to v1.0 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | hw/riscv: virt: Allow support for 32 cores Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | hw/riscv: Use error_fatal for SoC realisation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | target/riscv: Enable the Hypervisor extension by default Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | target/riscv: Mark the Hypervisor extension as non... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | hw/intc: sifive_plic: Cleanup remaining functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | hw/intc: sifive_plic: Cleanup the read function Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | hw/intc: sifive_plic: Cleanup the write function Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Alistair Francis | hw/intc: sifive_plic: Add a reset function Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Jim Shu | hw/dma: sifive_pdma: permit 4/8-byte access size of... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Jim Shu | hw/dma: sifive_pdma: support high 32-bit access of... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2022-01-08 | Nikita Shubin | target/riscv/pmp: fix no pmp illegal intrs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-12-20 | Jessica Clarke | hw/riscv: Use load address rather than entry point... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-12-20 | Vineet Gupta | target/riscv: Enable bitmanip Zb[abcs] instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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