| commit | 6bf4bbed205127f3805e960a1213c2289db89114 | |
| author | Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> | |
| Thu, 6 Jan 2022 21:01:02 +0000 (6 22:01 +0100) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Sat, 8 Jan 2022 05:46:10 +0000 (8 15:46 +1000) | ||
| tree | 0b2772863db054b3e1fe1ce754c59c08d878618d | treesnapshot (tar.gz zip) |
| parent | 57c108b86461a050a58b1ca9d31fd6e4af32205c | commitdiff |
target/riscv: support for 128-bit shift instructions
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>