| commit | 13dbc826fd086dd40b7a4d3f1cb3f1bc8454b586 | |
| author | Frank Chang <frank.chang@sifive.com> | |
| Tue, 18 Jan 2022 01:45:08 +0000 (18 09:45 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 21 Jan 2022 05:52:56 +0000 (21 15:52 +1000) | ||
| tree | 760312d17640ab9bf584041180efe0fef989b7c7 | treesnapshot (tar.gz zip) |
| parent | aaae69942f5c73a724daf09dcbd963cd852ccb64 | commitdiff |
target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/insn_trans/trans_rvv.c.inc | diffblobblamehistory |