target/riscv: array for the 64 upper bits of 128-bit registers
commit2b5470843a6bf10bcc4431d81badec6bfe31f0a7
authorFrédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Thu, 6 Jan 2022 21:00:56 +0000 (6 22:00 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 8 Jan 2022 05:46:10 +0000 (8 15:46 +1000)
tree444313b9acadb43ce1956a288ac5709210e6e9a7
parenta1a3aac448cced3161cd0c8a49ac24cd5d58fe14
target/riscv: array for the 64 upper bits of 128-bit registers

The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-7-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/machine.c
target/riscv/translate.c