RISC-V: Implement instruction patterns for ZBB extension.
2021-10-25 Jim Wilson <jimw@sifive.com>
Kito Cheng <kito.cheng@sifive.com>
Jia-Wei Chen <jiawei@iscas.ac.cn>
gcc/ChangeLog:
* config/riscv/bitmanip.md (bitmanip_bitwise): New.
(bitmanip_minmax): New.
(clz_ctz_pcnt): New.
(bitmanip_optab): New.
(bitmanip_insn): New.
(*<optab>_not<mode>): New.
(*xor_not<mode>): New.
(<bitmanip_optab>si2): New.
(*<bitmanip_optab>disi2): New.
(<bitmanip_optab>di2): New.
(*zero_extendhi<GPR:mode>2_bitmanip): New.
(*extend<SHORT:mode><SUPERQI:mode>2_zbb): New.
(*zero_extendhi<GPR:mode>2_zbb): New.
(rotrsi3): New.
(rotrdi3): New.
(rotrsi3_sext): New.
(rotlsi3): New.
(rotldi3): New.
(rotlsi3_sext): New.
(bswap<mode>2): New.
(<bitmanip_optab><mode>3): New.
* config/riscv/riscv.md (type): Add rotate.
(zero_extendhi<GPR:mode>2): Change to define_expand pattern.
(*zero_extendhi<GPR:mode>2): New.
(extend<SHORT:mode><SUPERQI:mode>2): Change to define_expand pattern.
(*extend<SHORT:mode><SUPERQI:mode>2): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-andn-orn-xnor-01.c: New.
* gcc.target/riscv/zbb-andn-orn-xnor-02.c: Ditto.
* gcc.target/riscv/zbb-min-max.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-01.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-02.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-03.c: Ditto.
* gcc.target/riscv/zbbw.c: Ditto.
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Co-authored-by: Jia-Wei Chen <jiawei@iscas.ac.cn>