RISC-V: Implement instruction patterns for ZBB extension.
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / zbb-andn-orn-xnor-01.c
blob0037dea5647aeb9e86cdbebe51bf59bf4c7a6a8b
1 /* { dg-do compile } */
2 /* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
4 unsigned long long foo1(unsigned long long rs1, unsigned long long rs2)
6 return rs1 & ~rs2;
9 unsigned long long foo2(unsigned long long rs1, unsigned long long rs2)
11 return rs1 | ~rs2;
14 unsigned long long foo3(unsigned long long rs1, unsigned long long rs2)
16 return rs1 ^ ~rs2;
19 /* { dg-final { scan-assembler-times "andn" 2 } } */
20 /* { dg-final { scan-assembler-times "orn" 2 } } */
21 /* { dg-final { scan-assembler-times "xnor" 2 } } */