RISC-V: Implement instruction patterns for ZBB extension.
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / zbb-andn-orn-xnor-02.c
blobb0c1e40c554607022e805357dd3c25f1f78bf997
1 /* { dg-do compile } */
2 /* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
4 unsigned int foo1(unsigned int rs1, unsigned int rs2)
6 return rs1 & ~rs2;
9 unsigned int foo2(unsigned int rs1, unsigned int rs2)
11 return rs1 | ~rs2;
14 unsigned int foo3(unsigned int rs1, unsigned int rs2)
16 return rs1 ^ ~rs2;
19 /* { dg-final { scan-assembler-times "andn" 2 } } */
20 /* { dg-final { scan-assembler-times "orn" 2 } } */
21 /* { dg-final { scan-assembler-times "xnor" 2 } } */