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3rdparty/opensbi: Add submodule
2019-04-08 Mario Scheithauersiemens/mc_apl5: Remove reduced clock rate for I2C0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2019-03-08 Mario Scheithauersrc/soc/intel/apollolake/cpu.c: Set up local APIC
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2019-03-03 Mario Scheithauersb/intel/common/firmware: Don't touch descriptor region
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2019-02-13 Mario Scheithauersiemens/mc_apl2: Remove double entry from devicetree
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2019-01-30 Mario Scheithauersiemens/mc_apl2: Change SERIRQ mode
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2019-01-30 Mario Scheithauersiemens/mc_apl2: Correct whitespace of devicetree
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2019-01-30 Mario Scheithauersiemens/mc_apl2: Activate TPM support
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2019-01-16 Mario Scheithauersiemens/mc_apl4: Change UART_FOR_CONSOLE index
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2019-01-11 Mario Scheithauersiemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLE
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-29 Mario Scheithauersiemens/mc_apl5: Disable PCI clock outputs on XIO bridges
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-29 Mario Scheithauersiemens/mc_apl5: Set bus master bit for on-board PCI...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-29 Mario Scheithauersiemens/mc_apl5: Enable SDCARD
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-27 Mario Scheithauersiemens/mc_apl5: Adjust the settings for the PCIe root...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-26 Mario Scheithauersiemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-18 Mario Scheithauersiemens/mc_apl5: Add new mainboard variant mc_apl5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-16 Mario Scheithauersiemens/mc_apl4: Clean up ramstage
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-16 Mario Scheithauersiemens/mc_apl4: Overwrite swizzle data for LPDDR4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-12 Mario Scheithauersiemens/mc_apl4: Enable SDCARD
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-12 Mario Scheithauersiemens/mc_apl4: Remove external RTC from I2C0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-12 Mario Scheithauersiemens/mc_apl4: Enable all PCIe root ports
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-12 Mario Scheithauersiemens/mc_apl4: Remove reduced clock rate for I2C0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-12 Mario Scheithauersiemens/mc_apl4: Disable CLKREQ of PCIe root ports
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-12 Mario Scheithauersiemens/mc_apl3: Disable PCI clock outputs on XIO bridges
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-12 Mario Scheithauersiemens/mc_apl3: Set Full Reset Bit into Reset Control...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-12 Mario Scheithauersiemens/mc_apl3: Set bus master bit for on-board PCI...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-12 Mario Scheithauersiemens/mc_apl3: Remove the correction of the Tx signal...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-12 Mario Scheithauersiemens/mc_apl3: Adjust Legacy IRQ routing for PCI...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-07 Mario Scheithauersiemens/mc_apl4: Add new mainboard variant mc_apl4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-07 Mario Scheithauersiemens/mc_apl2: Adjust GPIO settings for mc_apl2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-07 Mario Scheithauersiemens/mc_apl3: Disable I2C7 over devicetree
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-07 Mario Scheithauersiemens/mc_apl3: Enable all PCIe root ports
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-07 Mario Scheithauersiemens/mc_apl3: Remove reduced clock rate for I2C0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-07 Mario Scheithauersiemens/mc_apl3: Disable CLKREQ of PCIe root ports
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-11-07 Mario Scheithauersiemens/mc_apl3: Adjust GPIO settings for mc_apl3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-10-30 Mario Scheithauersiemens/mc_apl3: Add new mainboard variant mc_apl3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-10-01 Mario Scheithauersiemens/mc_apl1: Activate clock spreading for PTN3460
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-09-27 Mario Scheithauersiemens/mc_apl1: Add new mainboard variant mc_apl2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-09-27 Mario Scheithauersiemens/mc_apl1: Make the DDR memory swizzle data configurable
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-08-31 Mario Scheithauersiemens/mc_apl1: Correct the Tx signal from SATA interface
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-08-28 Mario Scheithauersiemens/mc_apl1: Extend circuit life by clock gating...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-08-27 Mario Scheithauersiemens/mc_apl1: Disable PCI clock outputs on XIO bridge
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-08-24 Mario Scheithauersiemens/mc_apl1: Select DDR50 mode for eMMC
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-08-24 Mario Scheithauersoc/intel/apollolake: Make eMMC max speed configurable
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-08-23 Mario Scheithauersiemens/mc_apl1: Make adjustments for the 1st redesign...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-08-23 Mario Scheithauersiemens/mc_apl1: Move board specific things to mc_apl1...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-04-27 Mario Scheithauersiemens/mc_apl1: Move board specific things to mc_apl1...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-04-26 Mario Scheithauersiemens/mc_apl1: Provide baseboard and variant concepts
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-04-13 Mario Scheithauersiemens/mc_apl1: Fix accuracy issue with IDT PMIC
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-04-11 Mario Scheithauersiemens/mc_apl1: Make DRAM configuration more flexible
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2018-04-11 Mario Scheithauersoc/intel/common/block/cpu: Fix cpu_get_power_max
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-11-21 Mario Scheithauerarch/x86: Write ACPI DBG2 table only if the device...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-11-07 Mario Scheithauersiemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-11-07 Mario Scheithauersrc: Fix all Siemens copyrights
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-11-03 Mario Scheithauersoc/intel/apollolake: Add APL CPU device ID
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-11-03 Mario Scheithauersiemens/mc_apl1: Enable I2C0 with 100kHz
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-11-03 Mario Scheithauersiemens/mc_apl1: Set coreboot ready LED
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-11-03 Mario Scheithauersiemens/mc_apl1: Add legacy IRQ routing for PCI devices
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-11-03 Mario Scheithauersoc/intel/apollolake: Set CPU to Max Non-Turbo Ratio
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-09-28 Mario Scheithauersiemens/nc_fpga: Move some parameters to another function
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-09-21 Mario Scheithauersiemens/mc_apl1: Move SCI to IRQ 10
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-09-21 Mario Scheithauersoc/intel/apollolake: Make SCI configurable
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-09-08 Mario Scheithauersiemens/mc_apl1: Disable internal UARTs
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-09-08 Mario Scheithauersiemens/mc_apl1: Set bus master bit for on-board PCI...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-07-27 Mario Scheithauersiemens/mc_apl1: Select skip RAPL configuration
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-07-27 Mario Scheithauersoc/intel/apollolake: Make usage of RAPL selectable
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-07-20 Mario Scheithauersiemens/mc_apl1: Activate ECC for DRAM
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-07-20 Mario Scheithauersiemens/mc_apl1: Include platform.asl
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-07-20 Mario Scheithauersoc/intel/apollolake: Implement _PIC method into ACPI
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-07-18 Mario Scheithauersiemens/mc_apl1: Disable SDCARD
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-06-23 Mario Scheithauersiemens/mc_apl1: Enable decoding for COM 3 on LPC
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-06-23 Mario Scheithauersiemens/mc_apl1: Disable XDCI
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-06-13 Mario Scheithauersiemens/mc_apl1: Enable decoding for COM 3 on LPC
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-06-13 Mario Scheithauersiemens/mc_apl1: Use Siemens NC FPGA driver
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-06-13 Mario Scheithauersiemens/nc_fpga: Expand FPGA functionality
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-06-13 Mario Scheithauervendorcode/siemens: Add new values to hwilib
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-05-17 Mario Scheithauersiemens/mc_apl1: Program eMMC DLL settings
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-05-17 Mario Scheithauersiemens/mc_apl1: Select external 8250 UART
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-05-17 Mario Scheithauersoc/intel/apollolake: Enable decoding for ComA and...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-05-11 Mario Scheithauersiemens/mc_apl1: Add usage of external RTC RX6110 SA
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-05-11 Mario Scheithauerdrivers/i2c: Add new driver for RTC type RX6110 SA
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-05-11 Mario Scheithauersiemens/mc_apl1: Correct GPIO settings
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-04-04 Mario Scheithauersiemens/mc_apl1: Activate PTN3460 eDP to LVDS bridge IC
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-03-29 Mario Scheithauersiemens/mc_apl1: Adjust gpio settings
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-03-15 Mario Scheithauersiemens/mc_apl1: Clean up the code
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-02-20 Mario Scheithauersiemens/mc_apl1: Set MAC address for all available...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-02-15 Mario Scheithauersiemens/mc_apl1: Make basic settings for booting the...
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2017-02-02 Mario Scheithauersiemens/mc_apl1: Add new mainboard
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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