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description	Verilog Unit Test generator
homepage URL	http://www.cin.ufpe.br/~rjsp/vutg
owner	rodrigopex@gmail.com
last change	Thu, 8 May 2008 01:50:11 +0000 (7 22:50 -0300)
URL	git://repo.or.cz/vutg.git
	https://repo.or.cz/vutg.git
push URL	ssh://repo.or.cz/vutg.git
	https://repo.or.cz/vutg.git ^{(learn more)}
bundle info	vutg.git downloadable bundles
content tags add:	xnxx

readme

TODO:

2008-05-08	Rodrigo Peixoto	Improving text messages.master	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-25	Rodrigo Peixoto	run examples, more and more tests.	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-24	Rodrigo Peixoto	cleaningvutg-alpha-1	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-24	Rodrigo Peixoto	cleaning	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-24	Rodrigo Peixoto	Psyco optimize utilization.	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-24	Rodrigo Peixoto	cleaning	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-22	Rodrigo Peixoto	examples insertion.mob	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-20	Rodrigo Peixoto	more improvements.	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-18	Rodrigo Peixoto	improves	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-17	Rodrigo Peixoto	Generation code optmization.	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-14	Rodrigo Peixoto	Random alloc fixed!	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-13	Rodrigo Peixoto	Project cleaned, again.	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-13	Rodrigo Peixoto	Project cleaned.	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-10	Rodrigo Peixoto	Reference function ok!!!	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-09	Rodrigo Peixoto	Random generate done.	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
2008-04-09	Rodrigo Peixoto	wiki rev	commit \| commitdiff \| tree \| snapshot (tar.gz zip)
...

16 years ago

| commit | log

15 years ago	master	log \| tree
16 years ago	mob	log \| tree

Verilog Unit Test generator