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commit	0352dbab7698073fda84b133445159125a167a7c
author	Rodrigo Peixoto <rodrigopex@urano.(none)>
	Thu, 24 Apr 2008 01:56:59 +0000 (23 22:56 -0300)
committer	Rodrigo Peixoto <rodrigopex@urano.(none)>
	Thu, 24 Apr 2008 01:56:59 +0000 (23 22:56 -0300)
tree	a81584e6b160cc4056d22ffe14babe4a16ca3a08	tree \| snapshot (tar.gz zip)
parent	be7a65f275b14e299fed9c9f9f747b9ec04d4427	commit \| diff

Psyco optimize utilization.

13 files changed:

src/gen/a.mem	[new file with mode: 0644]	blob
src/gen/b.mem	[new file with mode: 0644]	blob
src/gen/overflow.mem	[new file with mode: 0644]	blob
src/gen/result.mem	[new file with mode: 0644]	blob
src/gen/vut_fulladder.v	[new file with mode: 0644]	blob
src/overflow.py		diff \| blob \| blame \| history
src/overflow.pyc		diff \| blob \| blame \| history
src/utils.py		diff \| blob \| blame \| history
src/utils.pyc		diff \| blob \| blame \| history
src/vut_checker.pyc		diff \| blob \| blame \| history
src/vut_front_end.pyc		diff \| blob \| blame \| history
src/vut_generator.pyc		diff \| blob \| blame \| history
src/vut_parser.pyc		diff \| blob \| blame \| history

Verilog Unit Test generator