Public Git Hosting - vutg.git/commit

commit	212554373b119bc61eeac419829abdaad366879b
author	Rodrigo Peixoto <rodrigopex@urano.(none)>
	Fri, 25 Apr 2008 00:45:09 +0000 (24 21:45 -0300)
committer	Rodrigo Peixoto <rodrigopex@urano.(none)>
	Fri, 25 Apr 2008 00:45:09 +0000 (24 21:45 -0300)
tree	a8ffabfa433cef895abb1acd2d05b0e990af9067	tree \| snapshot (tar.gz zip)
parent	ff78db40f1da3a5c039664403c90c03d10051411	commit \| diff

run examples, more and more tests.

57 files changed:

doc/.zim.cache	[moved from src/doc/.zim.cache with 100% similarity]	blob \| blame \| history
doc/.zim.config	[moved from src/doc/.zim.config with 100% similarity]	blob \| blame \| history
doc/.zim.history.cache	[moved from src/doc/.zim.history.cache with 100% similarity]	blob \| blame \| history
doc/VUTg.txt	[moved from src/doc/VUTg.txt with 100% similarity]	blob \| blame \| history
doc/grammar.txt	[moved from src/doc/grammar.txt with 100% similarity]	blob \| blame \| history
examples/fulladder/fulladder.vut	[copied from src/example6.vut with 100% similarity]	blob \| blame \| history
examples/fulladder/gen/fulladder.v	[new file with mode: 0644]	blob
examples/fulladder/gen/makefile	[moved from src/gen/makefile with 56% similarity]	diff \| blob \| blame \| history
examples/fulladder/gen/verilog.log	[copied from src/gen/verilog.log with 82% similarity]	diff \| blob \| blame \| history
examples/fulladder/overflow.py	[moved from src/overflow.py with 100% similarity]	blob \| blame \| history
examples/fulladder/overflow.pyc	[new file with mode: 0644]	blob
examples/register/gen/makefile	[moved from src/examples/register/gen/makefile with 56% similarity]	diff \| blob \| blame \| history
examples/register/gen/register8b.v	[copied from src/examples/register/gen/register8b.v with 88% similarity]	diff \| blob \| blame \| history
examples/register/gen/verilog.log	[moved from src/examples/register/gen/verilog.log with 72% similarity]	diff \| blob \| blame \| history
examples/register/out_data.py	[moved from src/examples/register/out_data.py with 62% similarity]	diff \| blob \| blame \| history
examples/register/out_data.pyc	[new file with mode: 0644]	blob
examples/register/register8b.vut	[moved from src/examples/register/register8b.vut with 81% similarity]	diff \| blob \| blame \| history
examples/register/register8b.v~	[moved from src/examples/register/register8b.v with 69% similarity]	diff \| blob \| blame \| history
examples/shifter/gen/makefile	[new file with mode: 0644]	blob
examples/shifter/gen/shifterR.v	[copied from src/examples/register/gen/register8b.v with 64% similarity]	diff \| blob \| blame \| history
examples/shifter/gen/verilog.log	[moved from src/gen/verilog.log with 59% similarity]	diff \| blob \| blame \| history
examples/shifter/out_data.py	[new file with mode: 0644]	blob
examples/shifter/out_data.pyc	[new file with mode: 0644]	blob
examples/shifter/shifterR.vut	[new file with mode: 0644]	blob
examples/shifter/shifterR.v~	[moved from src/examples/register/gen/register8b.v with 65% similarity]	diff \| blob \| blame \| history
examples/vutfiles/example1.vut	[moved from src/example1.vut with 100% similarity]	blob \| blame \| history
examples/vutfiles/example2.vut	[moved from src/example2.vut with 100% similarity]	blob \| blame \| history
examples/vutfiles/example3.vut	[moved from src/example3.vut with 100% similarity]	blob \| blame \| history
examples/vutfiles/example4.vut	[moved from src/example4.vut with 100% similarity]	blob \| blame \| history
examples/vutfiles/example5.vut	[moved from src/example5.vut with 100% similarity]	blob \| blame \| history
examples/vutfiles/example6.vut	[moved from src/example6.vut with 100% similarity]	blob \| blame \| history
examples/vutfiles/grammar.vut	[moved from src/grammar.vut with 100% similarity]	blob \| blame \| history
examples/vutfiles/teste.vut	[moved from src/teste.vut with 100% similarity]	blob \| blame \| history
src/examples/register/gen/clear.mem	[deleted file]	blob \| blame \| history
src/examples/register/gen/clk.mem	[deleted file]	blob \| blame \| history
src/examples/register/gen/in_data.mem	[deleted file]	blob \| blame \| history
src/examples/register/gen/load.mem	[deleted file]	blob \| blame \| history
src/examples/register/gen/out_data.mem	[deleted file]	blob \| blame \| history
src/examples/register/gen/vut_register8b.v	[deleted file]	blob \| blame \| history
src/examples/register/gen/waveform.vcd	[deleted file]	blob \| blame \| history
src/examples/register/o__init__.py	[deleted file]	blob \| blame \| history
src/examples/register/out_data.pyc	[deleted file]	blob \| blame \| history
src/overflow.pyc	[deleted file]	blob \| blame \| history
src/tags		diff \| blob \| blame \| history
src/testando.py	[deleted file]	blob \| blame \| history
src/utils.py		diff \| blob \| blame \| history
src/utils.pyc		diff \| blob \| blame \| history
src/verilog.log	[deleted file]	blob \| blame \| history
src/vut_checker.py		diff \| blob \| blame \| history
src/vut_checker.pyc		diff \| blob \| blame \| history
src/vut_front_end.py		diff \| blob \| blame \| history
src/vut_front_end.pyc		diff \| blob \| blame \| history
src/vut_generator.py		diff \| blob \| blame \| history
src/vut_generator.pyc		diff \| blob \| blame \| history
src/vut_parser.py		diff \| blob \| blame \| history
src/vut_parser.pyc		diff \| blob \| blame \| history
src/vutg		diff \| blob \| blame \| history

Verilog Unit Test generator

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