descriptionExperimental work
homepage URLhttp://github.com/ghdl/ghdl
ownertgingold@free.fr
last changeSun, 22 Jan 2023 11:07:39 +0000 (22 12:07 +0100)
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README.md

'Test' workflow Status

This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyse and elaborate sources for generating machine code from your design. Native program execution is the only way for high speed simulation.

Main features

Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions.

Partial support of PSL.

By using a code generator (LLVM, GCC or, x86_64/i386 only, a built-in one), it is much faster than any interpreted simulator. It can handle very large designs, such as leon3/grlib.

GHDL runs on GNU/Linux, Windows and macOS; on x86, x86_64, armv6/armv7/aarch32, aarch64 and ppc64. You can freely download nightly assets, use OCI images (aka Docker/Podman containers), or try building it on your own machine (see 'Getting GHDL' below).

Can write waveforms to GHW, VCD or FST files. Combined with a GUI-based waveform viewer and a good text editor, GHDL is a very powerful tool for writing, testing and simulating your code.

Co-simulation with foreign applications is supported through Verilog Procedural Interface (VPI) and/or VHPIDIRECT. See ghdl.github.io/ghdl-cosim.

Can synthesize arbitrarily complex VHDL designs into a VHDL 1993 netlist, which can be implicitly or explicitly used in open source or vendor synthesis frameworks.

Supported third party projects: Yosys (through ghdl-yosys-plugin), cocotb (through the VPI interface), OSVVM, UVVM, VUnit, ... (see ghdl/extended-tests).

GHDL is free software:

Getting GHDL

Project structure

Regular users

Advanced users

Codecov - Branch Coverage Codacy - Quality Codacy - Coverage

shortlog
2023-01-22 Tristan Gingoldverilog: add sv_maps iteratorsverilog
2023-01-22 Tristan Gingoldverilog: add a first test for associative arrays
2023-01-22 Tristan Gingoldverilog: add sv_maps
2023-01-22 Tristan Gingoldverilog: add a test for toupper
2023-01-22 Tristan Gingoldverilog: allocate all instantiated classes
2023-01-22 Tristan Gingoldverilog: add tests
2023-01-22 Tristan Gingoldverilog: refine constructor call
2023-01-22 Tristan Gingoldverilog: add a test for constructor
2023-01-22 Tristan Gingoldverilog: do not call super constructor twice.
2023-01-22 Tristan Gingoldverilog: add a test with assign operator
2023-01-22 Tristan Gingoldverilog: handle assign operator
2023-01-22 Tristan Gingoldverilog: add a test
2023-01-22 Tristan Gingoldverilog: use default values for implicit call to super...
2023-01-22 Tristan Gingoldverilog: handle more constructs
2023-01-22 Tristan Gingoldverilog: add uvm package
2023-01-22 Tristan Gingoldverilog: handle more vpi types
...
heads
15 months ago verilog