verilog: add a test with assign operator
commit106c76b8b3aacf51bed7e5255600fe5dedebb49b
authorTristan Gingold <tgingold@free.fr>
Mon, 24 Jan 2022 07:52:21 +0000 (24 08:52 +0100)
committerTristan Gingold <tgingold@free.fr>
Sun, 22 Jan 2023 11:07:36 +0000 (22 12:07 +0100)
tree094e5ca602ddf719925e9e155536ab821cb2eee1
parentfea9d303221f07c0f6e9dc5aedd718283af84973
verilog: add a test with assign operator
src/verilog/tests/08_classes/08_07_constructors/08_07_006.v [new file with mode: 0644]