verilog: add a test
commitc02f703b14180fed17f05b8cacef79dfdf07bcf2
authorTristan Gingold <tgingold@free.fr>
Sun, 23 Jan 2022 10:30:13 +0000 (23 11:30 +0100)
committerTristan Gingold <tgingold@free.fr>
Sun, 22 Jan 2023 11:07:35 +0000 (22 12:07 +0100)
treeb5c0102d935a352d98fed73fd1dc5a046fb3211a
parent30161c6ea9e1698cca3492bb7c0d8ba2067d6dee
verilog: add a test
src/verilog/tests/08_classes/08_07_constructors/08_07_005.v [new file with mode: 0644]