| commit | 3f171c1e01cd620c051d4fb0de1c6c04f8ccc4b8 | |
| author | Jeff Connelly <shellreef+git@gmail.com> | |
| Fri, 4 Jul 2008 20:49:47 +0000 (4 13:49 -0700) | ||
| committer | Jeff Connelly <shellreef+git@gmail.com> | |
| Fri, 4 Jul 2008 20:49:47 +0000 (4 13:49 -0700) | ||
| tree | a67092570b8be9734a4b02de4deb884cc6148b91 | treesnapshot (tar.gz zip) |
| parent | 83d9a5cec828d8ada126d7b651c65811b69c3d52 | commitdiff |
Move the inverter out of the clock generator (both versions) and into main.
Doing this so that the clock PCB netlist can be generated from
clock_gen.asc without needing to map the tinv to a CD4007 chip, by
running it through the pcb.py chip mapping program. The clock board could
now be generated directly from clock_gen.asy.
Doing this so that the clock PCB netlist can be generated from
clock_gen.asc without needing to map the tinv to a CD4007 chip, by
running it through the pcb.py chip mapping program. The clock board could
now be generated directly from clock_gen.asy.