From 3f171c1e01cd620c051d4fb0de1c6c04f8ccc4b8 Mon Sep 17 00:00:00 2001
From: Jeff Connelly <shellreef+git@gmail.com>
Date: Fri, 4 Jul 2008 13:49:47 -0700
Subject: [PATCH] Move the inverter out of the clock generator (both versions)
 and into main.

Doing this so that the clock PCB netlist can be generated from
clock_gen.asc without needing to map the tinv to a CD4007 chip, by
running it through the pcb.py chip mapping program. The clock board could
now be generated directly from clock_gen.asy.
---
 circuits/clock_gen-fast.asc |  8 +-------
 circuits/clock_gen-fast.asy |  8 +++-----
 circuits/clock_gen.asc      | 11 ++---------
 circuits/clock_gen.asy      |  9 +++------
 circuits/main.asc           | 11 ++++++++---
 circuits/main.plt           |  8 ++++----
 6 files changed, 21 insertions(+), 34 deletions(-)

diff --git a/circuits/clock_gen-fast.asc b/circuits/clock_gen-fast.asc
index 37e5d9e..8362d97 100755
--- a/circuits/clock_gen-fast.asc
+++ b/circuits/clock_gen-fast.asc
@@ -1,18 +1,12 @@
 Version 4
 SHEET 1 880 680
 WIRE 112 -48 80 -48
-WIRE 128 160 16 160
-WIRE 272 160 176 160
 FLAG 192 -48 0
-FLAG 80 -48 EXECUTE
-FLAG 16 160 EXECUTE
-FLAG 272 160 FETCH
+FLAG 80 -48 CLK
 SYMBOL voltage 96 -48 M90
 WINDOW 123 0 0 Left 0
 WINDOW 39 0 0 Left 0
 WINDOW 3 -78 187 VLeft 0
 SYMATTR Value PULSE(-5 5 30u 1n 1n 30u 60u)
 SYMATTR InstName VCLK
-SYMBOL sti 144 160 R0
-SYMATTR InstName invert_clk
 TEXT -64 -240 Left 0 ;2-phase clock generator.\nCould be physically realized with 555 timer.
diff --git a/circuits/clock_gen-fast.asy b/circuits/clock_gen-fast.asy
index 8d9d63f..f8eab6a 100755
--- a/circuits/clock_gen-fast.asy
+++ b/circuits/clock_gen-fast.asy
@@ -4,12 +4,10 @@ LINE Normal -80 0 80 0
 LINE Normal -80 0 -80 144
 LINE Normal -80 144 80 144
 LINE Normal 80 144 80 0
+TEXT -58 119 Left 0 Behavioral
 WINDOW 0 3 -15 Center 0
 WINDOW 3 -38 161 Left 0
 SYMATTR Description Trinary D-type master-slave flip-flop built using transmission gates and inverters
-PIN 80 48 RIGHT 4
-PINATTR PinName FETCH
+PIN 80 80 RIGHT 4
+PINATTR PinName CLK
 PINATTR SpiceOrder 1
-PIN 80 112 RIGHT 4
-PINATTR PinName EXECUTE
-PINATTR SpiceOrder 2
diff --git a/circuits/clock_gen.asc b/circuits/clock_gen.asc
index 5249242..9c5324e 100755
--- a/circuits/clock_gen.asc
+++ b/circuits/clock_gen.asc
@@ -11,16 +11,13 @@ WIRE 368 128 320 128
 WIRE 16 144 0 144
 WIRE 320 144 320 128
 WIRE 320 144 240 144
-WIRE -96 208 -208 208
-WIRE 16 208 -96 208
+WIRE 16 208 -208 208
 WIRE 272 208 240 208
 WIRE 368 208 272 208
 WIRE -16 272 -16 -32
 WIRE 16 272 -16 272
 WIRE 288 272 240 272
 WIRE 368 272 368 208
-WIRE -96 288 -96 208
-WIRE -96 288 -160 288
 WIRE 0 320 0 144
 WIRE 272 320 272 208
 WIRE 272 320 0 320
@@ -33,11 +30,9 @@ WIRE 368 400 368 336
 WIRE 368 400 288 400
 WIRE 400 400 368 400
 FLAG -176 400 $G_Vss
-FLAG -208 208 EXECUTE
+FLAG -208 208 CLK
 IOPIN -208 208 Out
 FLAG -176 -32 $G_Vdd
-FLAG -208 288 FETCH
-IOPIN -208 288 Out
 SYMBOL Misc\\NE555 128 176 R0
 SYMATTR InstName U1
 SYMBOL cap 272 320 R0
@@ -52,6 +47,4 @@ SYMATTR Value 3.3k
 SYMBOL res 352 32 R0
 SYMATTR InstName R1
 SYMATTR Value 330
-SYMBOL sti -176 288 M0
-SYMATTR InstName negCLK
 TEXT 48 464 Left 0 ;TODO: better frequency
diff --git a/circuits/clock_gen.asy b/circuits/clock_gen.asy
index a71bcc2..a32d05b 100755
--- a/circuits/clock_gen.asy
+++ b/circuits/clock_gen.asy
@@ -4,13 +4,10 @@ LINE Normal -80 0 80 0
 LINE Normal -80 0 -80 144
 LINE Normal -80 144 80 144
 LINE Normal 80 144 80 0
-TEXT -24 78 Left 0 555
+TEXT -18 125 Left 0 555
 WINDOW 0 3 -15 Center 0
 WINDOW 3 -38 161 Left 0
 SYMATTR Description Trinary D-type master-slave flip-flop built using transmission gates and inverters
-PIN 80 48 RIGHT 4
-PINATTR PinName FETCH
+PIN 80 80 RIGHT 4
+PINATTR PinName CLK
 PINATTR SpiceOrder 1
-PIN 80 112 RIGHT 4
-PINATTR PinName EXECUTE
-PINATTR SpiceOrder 2
diff --git a/circuits/main.asc b/circuits/main.asc
index c80bdfc..fa42f6d 100755
--- a/circuits/main.asc
+++ b/circuits/main.asc
@@ -90,14 +90,17 @@ WIRE 592 -480 544 -480
 WIRE 896 -464 848 -464
 WIRE 992 -464 944 -464
 WIRE 1040 -464 992 -464
-WIRE -320 -432 -368 -432
+WIRE -400 -432 -432 -432
+WIRE -320 -432 -352 -432
 WIRE 1040 -432 1040 -464
 WIRE 1072 -432 1040 -432
 WIRE 896 -400 848 -400
 WIRE 992 -400 944 -400
 WIRE 1072 -400 992 -400
 WIRE 208 -384 176 -384
-WIRE -320 -368 -368 -368
+WIRE -432 -368 -432 -432
+WIRE -432 -368 -480 -368
+WIRE -320 -368 -432 -368
 WIRE 320 -368 288 -368
 WIRE 384 -368 320 -368
 WIRE 1072 -368 1040 -368
@@ -205,7 +208,9 @@ SYMATTR InstName JUMP_MUX
 SYMBOL swrom-guess 256 -1104 R0
 WINDOW 0 43 -51 Left 0
 SYMATTR InstName SWROM
-SYMBOL clock_gen-fast -448 -480 R0
+SYMBOL sti -384 -432 R0
+SYMATTR InstName NEG_CLK
+SYMBOL clock_gen-fast -560 -448 R0
 SYMATTR InstName cg
 TEXT -8 -760 Left 0 !.tran 320u
 TEXT 736 -1192 Left 0 ;IN "Register"\n(User input)
diff --git a/circuits/main.plt b/circuits/main.plt
index aba5254..67dac02 100755
--- a/circuits/main.plt
+++ b/circuits/main.plt
@@ -99,18 +99,18 @@
    {
       traces: 3 {524301,0,"V(alu_in_b0)"} {524296,0,"V($g_vdd)"} {524297,0,"V($g_vss)"}
       X: ('µ',0,0,3e-005,0.00032)
-      Y[0]: (' ',0,-6,1,6)
+      Y[0]: (' ',0,-5,1,5)
       Y[1]: ('_',0,1e+308,0,-1e+308)
-      Volts: (' ',0,0,0,-6,1,6)
+      Volts: (' ',0,0,0,-5,1,5)
       Log: 0 0 0
       GridStyle: 1
    },
    {
       traces: 1 {524299,0,"V(execute)"}
       X: ('µ',0,0,3e-005,0.00032)
-      Y[0]: (' ',0,-6,1,6)
+      Y[0]: (' ',0,-5,1,5)
       Y[1]: ('_',0,1e+308,0,-1e+308)
-      Volts: (' ',0,0,0,-6,1,6)
+      Volts: (' ',0,0,0,-5,1,5)
       Log: 0 0 0
       GridStyle: 1
    },
-- 
2.11.4.GIT