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cpus.c: ensure running CPU recalculates icount deadlines on timer expiry
2018-03-29
Mic
h
ae
l
Clark
R
I
SC-V: Workaround
f
or critical ms
t
a
tus
.
F
S
bug
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-28
M
i
chael Clark
RISC-V
:
Fix incor
r
e
ct disassembly
for addiw
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-28
Michael Clark
RISC-V:
C
on
v
er
t
cpu defi
n
ition to future model
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-20
Michael Clark
RISC-V
:
Fix riscv_isa_stri
n
g
m
em
o
ry si
z
e
bug
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clar
k
RISC-V
Build Infrastructure
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
lark
SiFive Freedom U Serie
s
RISC-V Mac
h
ine
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael C
l
ark
SiFive Freedom E Series RIS
C
-V Machi
n
e
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
Si
F
ive RI
S
C-V PRCI Block
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
ael C
l
a
rk
S
iFiv
e
RISC-V
UART Dev
i
ce
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
i
chael
C
lark
RISC-V VirtI
O
M
a
chine
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
lark
S
iFiv
e
RISC-V T
e
st Finisher
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Cl
a
rk
RISC-V Spike Mac
h
i
n
es
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
ichael Clark
SiFive RISC-V PLIC B
l
ock
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
Clark
S
iFive
RISC-V CLIN
T
Block
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
ichael Clark
RISC-V HART
Array
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
RISC-V HTIF Console
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
ha
e
l
Clark
A
d
d symbol
table cal
l
back interface to load_
e
lf
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
ael
C
lark
RISC-V L
i
nux
User Emu
l
ati
o
n
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
i
chae
l
C
l
ark
RISC-V
P
h
y
sical Memor
y
Protection
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michae
l
Clar
k
RISC
-
V TCG C
o
d
e
Generation
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
lark
R
I
SC-
V
GDB Stub
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
RISC-V FPU
S
upp
o
rt
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
R
I
SC
-
V CPU
He
l
per
s
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
ael C
l
ark
RISC-V Di
s
assembler
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
RISC
-
V CPU Core Definition
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
Clark
RISC-V E
L
F Machine
D
e
finit
i
o
n
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-06
Michael Cl
a
rk
RISC-V Maintainers
Add
Michael Clark
, Palmer Dabbelt, Sagar Karandikar...
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree