| commit | 88a07990fa282e4b63845223e90d759ef6811264 | |
| author | Michael Clark <mjc@sifive.com> | |
| Fri, 2 Mar 2018 12:31:13 +0000 (3 01:31 +1300) | ||
| committer | Michael Clark <mjc@sifive.com> | |
| Tue, 6 Mar 2018 19:30:28 +0000 (7 08:30 +1300) | ||
| tree | 3d121bfa1fed1621a26b69f9534d7353c1509e5e | treesnapshot (tar.gz zip) |
| parent | 5b4beba1246ff163415bde41cd76935012b16823 | commitdiff |
SiFive RISC-V Test Finisher
Test finisher memory mapped device used to exit simulation.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Test finisher memory mapped device used to exit simulation.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
| hw/riscv/sifive_test.c | [new file with mode: 0644] | blob |
| include/hw/riscv/sifive_test.h | [new file with mode: 0644] | blob |