| commit | 0c3e702aca76ca6ebf2aac4451870efc9d52a7a3 | |
| author | Michael Clark <mjc@sifive.com> | |
| Fri, 2 Mar 2018 12:31:10 +0000 (3 01:31 +1300) | ||
| committer | Michael Clark <mjc@sifive.com> | |
| Tue, 6 Mar 2018 19:30:28 +0000 (7 08:30 +1300) | ||
| tree | 22aea5af273925447d74a25eca7ffe0e8f598526 | treesnapshot (tar.gz zip) |
| parent | ea10325917c8a8f92611025c85950c00f826cb73 | commitdiff |
RISC-V CPU Helpers
Privileged control and status register helpers and page fault handling.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
Privileged control and status register helpers and page fault handling.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
| target/riscv/helper.c | [new file with mode: 0644] | blob |
| target/riscv/helper.h | [new file with mode: 0644] | blob |
| target/riscv/op_helper.c | [new file with mode: 0644] | blob |