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hw/intc: sifive_plic: Drop PLICMode_H
2023-01-06 Bin Menghw/intc: sifive_plic: Drop PLICMode_H
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2023-01-06 Bin Menghw/riscv: spike: Remove misleading comments
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2023-01-06 Bin Menghw/riscv: Sort machines Kconfig options in alphabetical...
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2023-01-06 Bin Menghw/riscv: Fix opentitan dependency to SIFIVE_PLIC
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2023-01-06 Bin Menghw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt...
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2023-01-06 Bin Menghw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
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2023-01-06 Christoph MuellnerRISC-V: Add Zawrs ISA extension support
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2023-01-06 Bin Mengtarget/riscv: Clear mstatus.MPRV when leaving M-mode...
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2023-01-06 Bin Mengtarget/riscv: Simplify helper_sret() a little bit
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2023-01-06 Richard Hendersontarget/riscv: Set pc_succ_insn for !rvc illegal insn
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2023-01-06 Bin Mengtarget/riscv: Fix mret exception cause when no pmp...
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2023-01-06 Jim Shuhw/intc: sifive_plic: fix out-of-bound access of source_prio...
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2023-01-06 Conor Dooleyhw/{misc, riscv}: pfsoc: add system controller as unimplemented
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2023-01-06 Conor Dooleyhw/riscv: pfsoc: add missing FICs as unimplemented
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2023-01-06 Conor Dooleyhw/misc: pfsoc: add fabric clocks to ioscb
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2023-01-06 Bin Mengtarget/riscv: Add some comments for sstatus CSR in...
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2023-01-06 Jim Shutarget/riscv: support cache-related PMU events in virtual...
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2023-01-06 Atish Patrahw/riscv: virt: Remove the redundant ipi-id property
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2023-01-06 Anup Pateltarget/riscv: Typo fix in sstc() predicate
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2023-01-06 Frédéric Pétrothw/intc: sifive_plic: Renumber the S irqs for numa...
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2023-01-06 LIU Zhiweitarget/riscv: Add itrigger_enabled field to CPURISCVState
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2023-01-06 LIU Zhiweitarget/riscv: Enable native debug itrigger
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2023-01-06 LIU Zhiweitarget/riscv: Add itrigger support when icount is enabled
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2023-01-06 LIU Zhiweitarget/riscv: Add itrigger support when icount is not...
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2023-01-06 Mayuresh Chitaletarget/riscv: generate virtual instruction exception
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2023-01-06 Mayuresh Chitaletarget/riscv: smstateen check for h/s/envcfg
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2023-01-06 Mayuresh Chitaletarget/riscv: Add smstateen support
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2023-01-06 Wilfred Mallawahw/riscv/opentitan: add aon_timer base unimpl
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2023-01-06 Wilfred Mallawahw/riscv/opentitan: bump opentitan
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2023-01-06 Richard Hendersontcg/riscv: Fix base register for user-only qemu_ld/st
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2023-01-06 Richard Hendersontcg/riscv: Fix reg overlap case in tcg_out_addsub2
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2023-01-06 Richard Hendersontcg/riscv: Fix range matched by TCG_CT_CONST_M12
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2023-01-06 LIU Zhiweitarget/riscv: Fix PMP propagation for tlb
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2022-10-14 Alistair Francistarget/riscv: pmp: Fixup TLB size calculation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-10-14 Jim Shuhw/intc: sifive_plic: change interrupt priority register...
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2022-10-14 Jim Shuhw/intc: sifive_plic: fix hard-coded max priority level
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2022-10-14 Yang Liudisas/riscv.c: rvv: Add disas support for vector instructions
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2022-10-14 Sunil V Lhw/riscv: virt: Enable booting S-mode firmware from...
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2022-10-14 Sunil V Lhw/riscv: virt: Move create_fw_cfg() prior to loading...
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2022-10-14 Sunil V Lhw/arm, loongarch: Move load_image_to_fw_cfg() to common...
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2022-10-14 Wilfred Mallawahw/ssi: ibex_spi: fixup/add rw1c functionality
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2022-10-14 Wilfred Mallawahw/ssi: ibex_spi: fixup coverity issue
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2022-10-14 Bin Menghw/riscv: Update comment for qtest check in riscv_find_firmw...
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2022-09-27 Yang Liutarget/riscv: rvv-1.0: vf[w]redsum distinguish between...
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2022-09-27 Yang Liutarget/riscv: rvv-1.0: Simplify vfwredsum code
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2022-09-27 Frank Changtarget/riscv: debug: Add initial support of type 6...
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2022-09-27 Frank Changtarget/riscv: debug: Check VU/VS modes for type 2 trigger
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-27 Frank Changtarget/riscv: debug: Create common trigger actions...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-27 Frank Changtarget/riscv: debug: Introduce tinfo CSR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-27 Frank Changtarget/riscv: debug: Restrict the range of tselect...
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2022-09-27 Frank Changtarget/riscv: debug: Introduce tdata1, tdata2, and...
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2022-09-27 Frank Changtarget/riscv: debug: Introduce build_tdata1() to build...
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2022-09-27 Frank Changtarget/riscv: debug: Determine the trigger type from...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-26 Bernhard Beschowhw/riscv/sifive_e: Fix inheritance of SiFiveEState
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-26 Frank Changtarget/riscv: Check the correct exception cause in...
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2022-09-26 Alistair Francishw/riscv: opentitan: Expose the resetvec as a SoC property
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2022-09-26 Alistair Francishw/riscv: opentitan: Fixup resetvec
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-26 Alistair Francistarget/riscv: Set the CPU resetvec directly
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2022-09-26 Andrew Burgesstarget/riscv: remove fixed numbering from GDB xml feature...
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2022-09-26 Andrew Burgesstarget/riscv: remove fflags, frm, and fcsr from riscv...
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2022-09-26 Weiwei Litarget/riscv: fix csr check for cycle{h}, instret{h...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-26 Rahul Pathaktarget/riscv: Remove sideleg and sedeleg
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2022-09-26 Alex Bennéedocs/system: clean up code escape for riscv virt platform
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2022-09-26 Wilfred Mallawahw/ssi: ibex_spi: update reg addr
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-26 Wilfred Mallawahw/ssi: ibex_spi: fixup typos in ibex_spi_host
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patratarget/riscv: Update the privilege field for sscofpmf...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patrahw/riscv: virt: Add PMU DT node to the device tree
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patratarget/riscv: Add few cache related PMU events
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patratarget/riscv: Simplify counter predicate function
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patratarget/riscv: Add sscofpmf extension support
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2022-09-07 Atish Patratarget/riscv: Add vstimecmp support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patratarget/riscv: Add stimecmp support
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patrahw/intc: Move mtimer/mtimecmp to aclint
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2022-09-07 Anup Pateltarget/riscv: Use official extension names for AIA...
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2022-09-07 Rahul Pathaktarget/riscv: Add xicondops in ISA entry
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2022-09-07 Conor Dooleyhw/core: fix platform bus node name
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2022-09-07 Conor Dooleyhw/riscv: virt: fix syscon subnode paths
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2022-09-07 Conor Dooleyhw/riscv: virt: fix the plic's address cells
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2022-09-07 Conor Dooleyhw/riscv: virt: fix uart node name
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2022-09-07 Atish Patratarget/riscv: Remove additional priv version check...
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2022-09-07 Conor Dooleyhw/riscv: microchip_pfsoc: fix kernel panics due to...
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2022-09-07 Wilfred Mallawahw/riscv: opentitan: bump opentitan version
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2022-09-07 Weiwei Litarget/riscv: Fix priority of csr related check in...
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2022-09-07 Daniel Henrique... hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()
Cc: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Dao Lutarget/riscv: Add Zihintpause support
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2022-09-07 eopXDtarget/riscv: rvv: Add option 'rvv_ma_all_1s' to enable...
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector permutation...
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector mask...
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector floating...
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector fix...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector integer...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector integer...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vx instructions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector load...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vv instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2022-09-07 Bin Mengdocs: List kvm as a supported accelerator on RISC-V
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Alexey Baturotarget/riscv: Fix typo and restore Pointer Masking...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Bin Mengroms/opensbi: Upgrade from v1.0 to v1.1
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2022-09-07 Weiwei Litarget/riscv: Simplify the check in hmode to reuse...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2022-09-07 Weiwei Litarget/riscv: Fix checks in hmode/hmode32
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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