| commit | 6535a443345d659882444f0db1fafd22ba1f803a | |
| author | Anup Patel <apatel@ventanamicro.com> | |
| Tue, 8 Nov 2022 12:56:59 +0000 (8 18:26 +0530) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 6 Jan 2023 00:42:55 +0000 (6 10:42 +1000) | ||
| tree | 97974901476d3fb8db6ed0171f3066e978019071 | treesnapshot (tar.gz zip) |
| parent | 0a9a6cba8b9cad8786670fd8c9fa1b0d39bd00e8 | commitdiff |
target/riscv: Typo fix in sstc() predicate
We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/csr.c | diffblobblamehistory |