target/riscv/cpu_helper.c

   1 /*
   2  * RISC-V CPU helpers for qemu.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "qemu/main-loop.h"
  23 #include "cpu.h"
  24 #include "exec/exec-all.h"
  25 #include "tcg/tcg-op.h"
  26 #include "trace.h"
  27
  28 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
  29 {
  30 #ifdef CONFIG_USER_ONLY
  31     return 0;
  32 #else
  33     return env->priv;
  34 #endif
  35 }
  36
  37 #ifndef CONFIG_USER_ONLY
  38 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
  39 {
  40     target_ulong irqs;
  41
  42     target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
  43     target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
  44     target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE);
  45
  46     target_ulong pending = env->mip & env->mie &
  47                                ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
  48     target_ulong vspending = (env->mip & env->mie &
  49                               (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
  50
  51     target_ulong mie    = env->priv < PRV_M ||
  52                           (env->priv == PRV_M && mstatus_mie);
  53     target_ulong sie    = env->priv < PRV_S ||
  54                           (env->priv == PRV_S && mstatus_sie);
  55     target_ulong hs_sie = env->priv < PRV_S ||
  56                           (env->priv == PRV_S && hs_mstatus_sie);
  57
  58     if (riscv_cpu_virt_enabled(env)) {
  59         target_ulong pending_hs_irq = pending & -hs_sie;
  60
  61         if (pending_hs_irq) {
  62             riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
  63             return ctz64(pending_hs_irq);
  64         }
  65
  66         pending = vspending;
  67     }
  68
  69     irqs = (pending & ~env->mideleg & -mie) | (pending &  env->mideleg & -sie);
  70
  71     if (irqs) {
  72         return ctz64(irqs); /* since non-zero */
  73     } else {
  74         return EXCP_NONE; /* indicates no pending interrupt */
  75     }
  76 }
  77 #endif
  78
  79 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  80 {
  81 #if !defined(CONFIG_USER_ONLY)
  82     if (interrupt_request & CPU_INTERRUPT_HARD) {
  83         RISCVCPU *cpu = RISCV_CPU(cs);
  84         CPURISCVState *env = &cpu->env;
  85         int interruptno = riscv_cpu_local_irq_pending(env);
  86         if (interruptno >= 0) {
  87             cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
  88             riscv_cpu_do_interrupt(cs);
  89             return true;
  90         }
  91     }
  92 #endif
  93     return false;
  94 }
  95
  96 #if !defined(CONFIG_USER_ONLY)
  97
  98 /* Return true is floating point support is currently enabled */
  99 bool riscv_cpu_fp_enabled(CPURISCVState *env)
 100 {
 101     if (env->mstatus & MSTATUS_FS) {
 102         if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
 103             return false;
 104         }
 105         return true;
 106     }
 107
 108     return false;
 109 }
 110
 111 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
 112 {
 113     uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
 114                             MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
 115                             MSTATUS64_UXL;
 116     bool current_virt = riscv_cpu_virt_enabled(env);
 117
 118     g_assert(riscv_has_ext(env, RVH));
 119
 120     if (current_virt) {
 121         /* Current V=1 and we are about to change to V=0 */
 122         env->vsstatus = env->mstatus & mstatus_mask;
 123         env->mstatus &= ~mstatus_mask;
 124         env->mstatus |= env->mstatus_hs;
 125
 126         env->vstvec = env->stvec;
 127         env->stvec = env->stvec_hs;
 128
 129         env->vsscratch = env->sscratch;
 130         env->sscratch = env->sscratch_hs;
 131
 132         env->vsepc = env->sepc;
 133         env->sepc = env->sepc_hs;
 134
 135         env->vscause = env->scause;
 136         env->scause = env->scause_hs;
 137
 138         env->vstval = env->sbadaddr;
 139         env->sbadaddr = env->stval_hs;
 140
 141         env->vsatp = env->satp;
 142         env->satp = env->satp_hs;
 143     } else {
 144         /* Current V=0 and we are about to change to V=1 */
 145         env->mstatus_hs = env->mstatus & mstatus_mask;
 146         env->mstatus &= ~mstatus_mask;
 147         env->mstatus |= env->vsstatus;
 148
 149         env->stvec_hs = env->stvec;
 150         env->stvec = env->vstvec;
 151
 152         env->sscratch_hs = env->sscratch;
 153         env->sscratch = env->vsscratch;
 154
 155         env->sepc_hs = env->sepc;
 156         env->sepc = env->vsepc;
 157
 158         env->scause_hs = env->scause;
 159         env->scause = env->vscause;
 160
 161         env->stval_hs = env->sbadaddr;
 162         env->sbadaddr = env->vstval;
 163
 164         env->satp_hs = env->satp;
 165         env->satp = env->vsatp;
 166     }
 167 }
 168
 169 bool riscv_cpu_virt_enabled(CPURISCVState *env)
 170 {
 171     if (!riscv_has_ext(env, RVH)) {
 172         return false;
 173     }
 174
 175     return get_field(env->virt, VIRT_ONOFF);
 176 }
 177
 178 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
 179 {
 180     if (!riscv_has_ext(env, RVH)) {
 181         return;
 182     }
 183
 184     /* Flush the TLB on all virt mode changes. */
 185     if (get_field(env->virt, VIRT_ONOFF) != enable) {
 186         tlb_flush(env_cpu(env));
 187     }
 188
 189     env->virt = set_field(env->virt, VIRT_ONOFF, enable);
 190 }
 191
 192 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
 193 {
 194     if (!riscv_has_ext(env, RVH)) {
 195         return false;
 196     }
 197
 198     return get_field(env->virt, FORCE_HS_EXCEP);
 199 }
 200
 201 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
 202 {
 203     if (!riscv_has_ext(env, RVH)) {
 204         return;
 205     }
 206
 207     env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
 208 }
 209
 210 bool riscv_cpu_two_stage_lookup(int mmu_idx)
 211 {
 212     return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
 213 }
 214
 215 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
 216 {
 217     CPURISCVState *env = &cpu->env;
 218     if (env->miclaim & interrupts) {
 219         return -1;
 220     } else {
 221         env->miclaim |= interrupts;
 222         return 0;
 223     }
 224 }
 225
 226 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
 227 {
 228     CPURISCVState *env = &cpu->env;
 229     CPUState *cs = CPU(cpu);
 230     uint32_t old = env->mip;
 231     bool locked = false;
 232
 233     if (!qemu_mutex_iothread_locked()) {
 234         locked = true;
 235         qemu_mutex_lock_iothread();
 236     }
 237
 238     env->mip = (env->mip & ~mask) | (value & mask);
 239
 240     if (env->mip) {
 241         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 242     } else {
 243         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 244     }
 245
 246     if (locked) {
 247         qemu_mutex_unlock_iothread();
 248     }
 249
 250     return old;
 251 }
 252
 253 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
 254                              uint32_t arg)
 255 {
 256     env->rdtime_fn = fn;
 257     env->rdtime_fn_arg = arg;
 258 }
 259
 260 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
 261 {
 262     if (newpriv > PRV_M) {
 263         g_assert_not_reached();
 264     }
 265     if (newpriv == PRV_H) {
 266         newpriv = PRV_U;
 267     }
 268     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
 269     env->priv = newpriv;
 270
 271     /*
 272      * Clear the load reservation - otherwise a reservation placed in one
 273      * context/process can be used by another, resulting in an SC succeeding
 274      * incorrectly. Version 2.2 of the ISA specification explicitly requires
 275      * this behaviour, while later revisions say that the kernel "should" use
 276      * an SC instruction to force the yielding of a load reservation on a
 277      * preemptive context switch. As a result, do both.
 278      */
 279     env->load_res = -1;
 280 }
 281
 282 /* get_physical_address - get the physical address for this virtual address
 283  *
 284  * Do a page table walk to obtain the physical address corresponding to a
 285  * virtual address. Returns 0 if the translation was successful
 286  *
 287  * Adapted from Spike's mmu_t::translate and mmu_t::walk
 288  *
 289  * @env: CPURISCVState
 290  * @physical: This will be set to the calculated physical address
 291  * @prot: The returned protection attributes
 292  * @addr: The virtual address to be translated
 293  * @fault_pte_addr: If not NULL, this will be set to fault pte address
 294  *                  when a error occurs on pte address translation.
 295  *                  This will already be shifted to match htval.
 296  * @access_type: The type of MMU access
 297  * @mmu_idx: Indicates current privilege level
 298  * @first_stage: Are we in first stage translation?
 299  *               Second stage is used for hypervisor guest translation
 300  * @two_stage: Are we going to perform two stage translation
 301  */
 302 static int get_physical_address(CPURISCVState *env, hwaddr *physical,
 303                                 int *prot, target_ulong addr,
 304                                 target_ulong *fault_pte_addr,
 305                                 int access_type, int mmu_idx,
 306                                 bool first_stage, bool two_stage)
 307 {
 308     /* NOTE: the env->pc value visible here will not be
 309      * correct, but the value visible to the exception handler
 310      * (riscv_cpu_do_interrupt) is correct */
 311     MemTxResult res;
 312     MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
 313     int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
 314     bool use_background = false;
 315
 316     /*
 317      * Check if we should use the background registers for the two
 318      * stage translation. We don't need to check if we actually need
 319      * two stage translation as that happened before this function
 320      * was called. Background registers will be used if the guest has
 321      * forced a two stage translation to be on (in HS or M mode).
 322      */
 323     if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
 324         use_background = true;
 325     }
 326
 327     if (mode == PRV_M && access_type != MMU_INST_FETCH) {
 328         if (get_field(env->mstatus, MSTATUS_MPRV)) {
 329             mode = get_field(env->mstatus, MSTATUS_MPP);
 330         }
 331     }
 332
 333     if (first_stage == false) {
 334         /* We are in stage 2 translation, this is similar to stage 1. */
 335         /* Stage 2 is always taken as U-mode */
 336         mode = PRV_U;
 337     }
 338
 339     if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
 340         *physical = addr;
 341         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 342         return TRANSLATE_SUCCESS;
 343     }
 344
 345     *prot = 0;
 346
 347     hwaddr base;
 348     int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
 349
 350     if (first_stage == true) {
 351         mxr = get_field(env->mstatus, MSTATUS_MXR);
 352     } else {
 353         mxr = get_field(env->vsstatus, MSTATUS_MXR);
 354     }
 355
 356     if (first_stage == true) {
 357         if (use_background) {
 358             base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
 359             vm = get_field(env->vsatp, SATP_MODE);
 360         } else {
 361             base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
 362             vm = get_field(env->satp, SATP_MODE);
 363         }
 364         widened = 0;
 365     } else {
 366         base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
 367         vm = get_field(env->hgatp, HGATP_MODE);
 368         widened = 2;
 369     }
 370     /* status.SUM will be ignored if execute on background */
 371     sum = get_field(env->mstatus, MSTATUS_SUM) || use_background;
 372     switch (vm) {
 373     case VM_1_10_SV32:
 374       levels = 2; ptidxbits = 10; ptesize = 4; break;
 375     case VM_1_10_SV39:
 376       levels = 3; ptidxbits = 9; ptesize = 8; break;
 377     case VM_1_10_SV48:
 378       levels = 4; ptidxbits = 9; ptesize = 8; break;
 379     case VM_1_10_SV57:
 380       levels = 5; ptidxbits = 9; ptesize = 8; break;
 381     case VM_1_10_MBARE:
 382         *physical = addr;
 383         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 384         return TRANSLATE_SUCCESS;
 385     default:
 386       g_assert_not_reached();
 387     }
 388
 389     CPUState *cs = env_cpu(env);
 390     int va_bits = PGSHIFT + levels * ptidxbits + widened;
 391     target_ulong mask, masked_msbs;
 392
 393     if (TARGET_LONG_BITS > (va_bits - 1)) {
 394         mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
 395     } else {
 396         mask = 0;
 397     }
 398     masked_msbs = (addr >> (va_bits - 1)) & mask;
 399
 400     if (masked_msbs != 0 && masked_msbs != mask) {
 401         return TRANSLATE_FAIL;
 402     }
 403
 404     int ptshift = (levels - 1) * ptidxbits;
 405     int i;
 406
 407 #if !TCG_OVERSIZED_GUEST
 408 restart:
 409 #endif
 410     for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
 411         target_ulong idx;
 412         if (i == 0) {
 413             idx = (addr >> (PGSHIFT + ptshift)) &
 414                            ((1 << (ptidxbits + widened)) - 1);
 415         } else {
 416             idx = (addr >> (PGSHIFT + ptshift)) &
 417                            ((1 << ptidxbits) - 1);
 418         }
 419
 420         /* check that physical address of PTE is legal */
 421         hwaddr pte_addr;
 422
 423         if (two_stage && first_stage) {
 424             int vbase_prot;
 425             hwaddr vbase;
 426
 427             /* Do the second stage translation on the base PTE address. */
 428             int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
 429                                                  base, NULL, MMU_DATA_LOAD,
 430                                                  mmu_idx, false, true);
 431
 432             if (vbase_ret != TRANSLATE_SUCCESS) {
 433                 if (fault_pte_addr) {
 434                     *fault_pte_addr = (base + idx * ptesize) >> 2;
 435                 }
 436                 return TRANSLATE_G_STAGE_FAIL;
 437             }
 438
 439             pte_addr = vbase + idx * ptesize;
 440         } else {
 441             pte_addr = base + idx * ptesize;
 442         }
 443
 444         if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 445             !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
 446             1 << MMU_DATA_LOAD, PRV_S)) {
 447             return TRANSLATE_PMP_FAIL;
 448         }
 449
 450 #if defined(TARGET_RISCV32)
 451         target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
 452 #elif defined(TARGET_RISCV64)
 453         target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
 454 #endif
 455         if (res != MEMTX_OK) {
 456             return TRANSLATE_FAIL;
 457         }
 458
 459         hwaddr ppn = pte >> PTE_PPN_SHIFT;
 460
 461         if (!(pte & PTE_V)) {
 462             /* Invalid PTE */
 463             return TRANSLATE_FAIL;
 464         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
 465             /* Inner PTE, continue walking */
 466             base = ppn << PGSHIFT;
 467         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
 468             /* Reserved leaf PTE flags: PTE_W */
 469             return TRANSLATE_FAIL;
 470         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
 471             /* Reserved leaf PTE flags: PTE_W + PTE_X */
 472             return TRANSLATE_FAIL;
 473         } else if ((pte & PTE_U) && ((mode != PRV_U) &&
 474                    (!sum || access_type == MMU_INST_FETCH))) {
 475             /* User PTE flags when not U mode and mstatus.SUM is not set,
 476                or the access type is an instruction fetch */
 477             return TRANSLATE_FAIL;
 478         } else if (!(pte & PTE_U) && (mode != PRV_S)) {
 479             /* Supervisor PTE flags when not S mode */
 480             return TRANSLATE_FAIL;
 481         } else if (ppn & ((1ULL << ptshift) - 1)) {
 482             /* Misaligned PPN */
 483             return TRANSLATE_FAIL;
 484         } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
 485                    ((pte & PTE_X) && mxr))) {
 486             /* Read access check failed */
 487             return TRANSLATE_FAIL;
 488         } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
 489             /* Write access check failed */
 490             return TRANSLATE_FAIL;
 491         } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
 492             /* Fetch access check failed */
 493             return TRANSLATE_FAIL;
 494         } else {
 495             /* if necessary, set accessed and dirty bits. */
 496             target_ulong updated_pte = pte | PTE_A |
 497                 (access_type == MMU_DATA_STORE ? PTE_D : 0);
 498
 499             /* Page table updates need to be atomic with MTTCG enabled */
 500             if (updated_pte != pte) {
 501                 /*
 502                  * - if accessed or dirty bits need updating, and the PTE is
 503                  *   in RAM, then we do so atomically with a compare and swap.
 504                  * - if the PTE is in IO space or ROM, then it can't be updated
 505                  *   and we return TRANSLATE_FAIL.
 506                  * - if the PTE changed by the time we went to update it, then
 507                  *   it is no longer valid and we must re-walk the page table.
 508                  */
 509                 MemoryRegion *mr;
 510                 hwaddr l = sizeof(target_ulong), addr1;
 511                 mr = address_space_translate(cs->as, pte_addr,
 512                     &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
 513                 if (memory_region_is_ram(mr)) {
 514                     target_ulong *pte_pa =
 515                         qemu_map_ram_ptr(mr->ram_block, addr1);
 516 #if TCG_OVERSIZED_GUEST
 517                     /* MTTCG is not enabled on oversized TCG guests so
 518                      * page table updates do not need to be atomic */
 519                     *pte_pa = pte = updated_pte;
 520 #else
 521                     target_ulong old_pte =
 522                         qatomic_cmpxchg(pte_pa, pte, updated_pte);
 523                     if (old_pte != pte) {
 524                         goto restart;
 525                     } else {
 526                         pte = updated_pte;
 527                     }
 528 #endif
 529                 } else {
 530                     /* misconfigured PTE in ROM (AD bits are not preset) or
 531                      * PTE is in IO space and can't be updated atomically */
 532                     return TRANSLATE_FAIL;
 533                 }
 534             }
 535
 536             /* for superpage mappings, make a fake leaf PTE for the TLB's
 537                benefit. */
 538             target_ulong vpn = addr >> PGSHIFT;
 539             *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
 540                         (addr & ~TARGET_PAGE_MASK);
 541
 542             /* set permissions on the TLB entry */
 543             if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
 544                 *prot |= PAGE_READ;
 545             }
 546             if ((pte & PTE_X)) {
 547                 *prot |= PAGE_EXEC;
 548             }
 549             /* add write permission on stores or if the page is already dirty,
 550                so that we TLB miss on later writes to update the dirty bit */
 551             if ((pte & PTE_W) &&
 552                     (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
 553                 *prot |= PAGE_WRITE;
 554             }
 555             return TRANSLATE_SUCCESS;
 556         }
 557     }
 558     return TRANSLATE_FAIL;
 559 }
 560
 561 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 562                                 MMUAccessType access_type, bool pmp_violation,
 563                                 bool first_stage, bool two_stage)
 564 {
 565     CPUState *cs = env_cpu(env);
 566     int page_fault_exceptions;
 567     if (first_stage) {
 568         page_fault_exceptions =
 569             get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
 570             !pmp_violation;
 571     } else {
 572         page_fault_exceptions =
 573             get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
 574             !pmp_violation;
 575     }
 576     switch (access_type) {
 577     case MMU_INST_FETCH:
 578         if (riscv_cpu_virt_enabled(env) && !first_stage) {
 579             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
 580         } else {
 581             cs->exception_index = page_fault_exceptions ?
 582                 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
 583         }
 584         break;
 585     case MMU_DATA_LOAD:
 586         if (two_stage && !first_stage) {
 587             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
 588         } else {
 589             cs->exception_index = page_fault_exceptions ?
 590                 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
 591         }
 592         break;
 593     case MMU_DATA_STORE:
 594         if (two_stage && !first_stage) {
 595             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
 596         } else {
 597             cs->exception_index = page_fault_exceptions ?
 598                 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 599         }
 600         break;
 601     default:
 602         g_assert_not_reached();
 603     }
 604     env->badaddr = address;
 605 }
 606
 607 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 608 {
 609     RISCVCPU *cpu = RISCV_CPU(cs);
 610     CPURISCVState *env = &cpu->env;
 611     hwaddr phys_addr;
 612     int prot;
 613     int mmu_idx = cpu_mmu_index(&cpu->env, false);
 614
 615     if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
 616                              true, riscv_cpu_virt_enabled(env))) {
 617         return -1;
 618     }
 619
 620     if (riscv_cpu_virt_enabled(env)) {
 621         if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
 622                                  0, mmu_idx, false, true)) {
 623             return -1;
 624         }
 625     }
 626
 627     return phys_addr & TARGET_PAGE_MASK;
 628 }
 629
 630 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 631                                      vaddr addr, unsigned size,
 632                                      MMUAccessType access_type,
 633                                      int mmu_idx, MemTxAttrs attrs,
 634                                      MemTxResult response, uintptr_t retaddr)
 635 {
 636     RISCVCPU *cpu = RISCV_CPU(cs);
 637     CPURISCVState *env = &cpu->env;
 638
 639     if (access_type == MMU_DATA_STORE) {
 640         cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 641     } else {
 642         cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
 643     }
 644
 645     env->badaddr = addr;
 646     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 647 }
 648
 649 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 650                                    MMUAccessType access_type, int mmu_idx,
 651                                    uintptr_t retaddr)
 652 {
 653     RISCVCPU *cpu = RISCV_CPU(cs);
 654     CPURISCVState *env = &cpu->env;
 655     switch (access_type) {
 656     case MMU_INST_FETCH:
 657         cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
 658         break;
 659     case MMU_DATA_LOAD:
 660         cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
 661         break;
 662     case MMU_DATA_STORE:
 663         cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
 664         break;
 665     default:
 666         g_assert_not_reached();
 667     }
 668     env->badaddr = addr;
 669     riscv_raise_exception(env, cs->exception_index, retaddr);
 670 }
 671 #endif
 672
 673 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 674                         MMUAccessType access_type, int mmu_idx,
 675                         bool probe, uintptr_t retaddr)
 676 {
 677     RISCVCPU *cpu = RISCV_CPU(cs);
 678     CPURISCVState *env = &cpu->env;
 679 #ifndef CONFIG_USER_ONLY
 680     vaddr im_address;
 681     hwaddr pa = 0;
 682     int prot, prot2;
 683     bool pmp_violation = false;
 684     bool first_stage_error = true;
 685     bool two_stage_lookup = false;
 686     int ret = TRANSLATE_FAIL;
 687     int mode = mmu_idx;
 688     target_ulong tlb_size = 0;
 689
 690     env->guest_phys_fault_addr = 0;
 691
 692     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 693                   __func__, address, access_type, mmu_idx);
 694
 695     if (mode == PRV_M && access_type != MMU_INST_FETCH) {
 696         if (get_field(env->mstatus, MSTATUS_MPRV)) {
 697             mode = get_field(env->mstatus, MSTATUS_MPP);
 698         }
 699     }
 700
 701     if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
 702         access_type != MMU_INST_FETCH &&
 703         get_field(env->mstatus, MSTATUS_MPRV) &&
 704         get_field(env->mstatus, MSTATUS_MPV)) {
 705         two_stage_lookup = true;
 706     }
 707
 708     if (riscv_cpu_virt_enabled(env) ||
 709         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
 710          access_type != MMU_INST_FETCH)) {
 711         /* Two stage lookup */
 712         ret = get_physical_address(env, &pa, &prot, address,
 713                                    &env->guest_phys_fault_addr, access_type,
 714                                    mmu_idx, true, true);
 715
 716         /*
 717          * A G-stage exception may be triggered during two state lookup.
 718          * And the env->guest_phys_fault_addr has already been set in
 719          * get_physical_address().
 720          */
 721         if (ret == TRANSLATE_G_STAGE_FAIL) {
 722             first_stage_error = false;
 723             access_type = MMU_DATA_LOAD;
 724         }
 725
 726         qemu_log_mask(CPU_LOG_MMU,
 727                       "%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
 728                       TARGET_FMT_plx " prot %d\n",
 729                       __func__, address, ret, pa, prot);
 730
 731         if (ret == TRANSLATE_SUCCESS) {
 732             /* Second stage lookup */
 733             im_address = pa;
 734
 735             ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
 736                                        access_type, mmu_idx, false, true);
 737
 738             qemu_log_mask(CPU_LOG_MMU,
 739                     "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
 740                     TARGET_FMT_plx " prot %d\n",
 741                     __func__, im_address, ret, pa, prot2);
 742
 743             prot &= prot2;
 744
 745             if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 746                 (ret == TRANSLATE_SUCCESS) &&
 747                 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 748                 ret = TRANSLATE_PMP_FAIL;
 749             }
 750
 751             if (ret != TRANSLATE_SUCCESS) {
 752                 /*
 753                  * Guest physical address translation failed, this is a HS
 754                  * level exception
 755                  */
 756                 first_stage_error = false;
 757                 env->guest_phys_fault_addr = (im_address |
 758                                               (address &
 759                                                (TARGET_PAGE_SIZE - 1))) >> 2;
 760             }
 761         }
 762     } else {
 763         /* Single stage lookup */
 764         ret = get_physical_address(env, &pa, &prot, address, NULL,
 765                                    access_type, mmu_idx, true, false);
 766
 767         qemu_log_mask(CPU_LOG_MMU,
 768                       "%s address=%" VADDR_PRIx " ret %d physical "
 769                       TARGET_FMT_plx " prot %d\n",
 770                       __func__, address, ret, pa, prot);
 771     }
 772
 773     if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 774         (ret == TRANSLATE_SUCCESS) &&
 775         !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 776         ret = TRANSLATE_PMP_FAIL;
 777     }
 778     if (ret == TRANSLATE_PMP_FAIL) {
 779         pmp_violation = true;
 780     }
 781
 782     if (ret == TRANSLATE_SUCCESS) {
 783         if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
 784             tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
 785                          prot, mmu_idx, tlb_size);
 786         } else {
 787             tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
 788                          prot, mmu_idx, TARGET_PAGE_SIZE);
 789         }
 790         return true;
 791     } else if (probe) {
 792         return false;
 793     } else {
 794         raise_mmu_exception(env, address, access_type, pmp_violation,
 795                             first_stage_error,
 796                             riscv_cpu_virt_enabled(env) ||
 797                                 riscv_cpu_two_stage_lookup(mmu_idx));
 798         riscv_raise_exception(env, cs->exception_index, retaddr);
 799     }
 800
 801     return true;
 802
 803 #else
 804     switch (access_type) {
 805     case MMU_INST_FETCH:
 806         cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
 807         break;
 808     case MMU_DATA_LOAD:
 809         cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
 810         break;
 811     case MMU_DATA_STORE:
 812         cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
 813         break;
 814     default:
 815         g_assert_not_reached();
 816     }
 817     env->badaddr = address;
 818     cpu_loop_exit_restore(cs, retaddr);
 819 #endif
 820 }
 821
 822 /*
 823  * Handle Traps
 824  *
 825  * Adapted from Spike's processor_t::take_trap.
 826  *
 827  */
 828 void riscv_cpu_do_interrupt(CPUState *cs)
 829 {
 830 #if !defined(CONFIG_USER_ONLY)
 831
 832     RISCVCPU *cpu = RISCV_CPU(cs);
 833     CPURISCVState *env = &cpu->env;
 834     bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env);
 835     uint64_t s;
 836
 837     /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
 838      * so we mask off the MSB and separate into trap type and cause.
 839      */
 840     bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
 841     target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
 842     target_ulong deleg = async ? env->mideleg : env->medeleg;
 843     bool write_tval = false;
 844     target_ulong tval = 0;
 845     target_ulong htval = 0;
 846     target_ulong mtval2 = 0;
 847
 848     if (!async) {
 849         /* set tval to badaddr for traps with address information */
 850         switch (cause) {
 851         case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
 852         case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
 853         case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
 854             force_hs_execp = true;
 855             /* fallthrough */
 856         case RISCV_EXCP_INST_ADDR_MIS:
 857         case RISCV_EXCP_INST_ACCESS_FAULT:
 858         case RISCV_EXCP_LOAD_ADDR_MIS:
 859         case RISCV_EXCP_STORE_AMO_ADDR_MIS:
 860         case RISCV_EXCP_LOAD_ACCESS_FAULT:
 861         case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
 862         case RISCV_EXCP_INST_PAGE_FAULT:
 863         case RISCV_EXCP_LOAD_PAGE_FAULT:
 864         case RISCV_EXCP_STORE_PAGE_FAULT:
 865             write_tval  = true;
 866             tval = env->badaddr;
 867             break;
 868         default:
 869             break;
 870         }
 871         /* ecall is dispatched as one cause so translate based on mode */
 872         if (cause == RISCV_EXCP_U_ECALL) {
 873             assert(env->priv <= 3);
 874
 875             if (env->priv == PRV_M) {
 876                 cause = RISCV_EXCP_M_ECALL;
 877             } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
 878                 cause = RISCV_EXCP_VS_ECALL;
 879             } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
 880                 cause = RISCV_EXCP_S_ECALL;
 881             } else if (env->priv == PRV_U) {
 882                 cause = RISCV_EXCP_U_ECALL;
 883             }
 884         }
 885     }
 886
 887     trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
 888                      riscv_cpu_get_trap_name(cause, async));
 889
 890     qemu_log_mask(CPU_LOG_INT,
 891                   "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
 892                   "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
 893                   __func__, env->mhartid, async, cause, env->pc, tval,
 894                   riscv_cpu_get_trap_name(cause, async));
 895
 896     if (env->priv <= PRV_S &&
 897             cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
 898         /* handle the trap in S-mode */
 899         if (riscv_has_ext(env, RVH)) {
 900             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
 901             bool two_stage_lookup = false;
 902
 903             if (env->priv == PRV_M ||
 904                 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 905                 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
 906                     get_field(env->hstatus, HSTATUS_HU))) {
 907                     two_stage_lookup = true;
 908             }
 909
 910             if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
 911                 /*
 912                  * If we are writing a guest virtual address to stval, set
 913                  * this to 1. If we are trapping to VS we will set this to 0
 914                  * later.
 915                  */
 916                 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1);
 917             } else {
 918                 /* For other HS-mode traps, we set this to 0. */
 919                 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
 920             }
 921
 922             if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
 923                 !force_hs_execp) {
 924                 /* Trap to VS mode */
 925                 /*
 926                  * See if we need to adjust cause. Yes if its VS mode interrupt
 927                  * no if hypervisor has delegated one of hs mode's interrupt
 928                  */
 929                 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
 930                     cause == IRQ_VS_EXT) {
 931                     cause = cause - 1;
 932                 }
 933                 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
 934             } else if (riscv_cpu_virt_enabled(env)) {
 935                 /* Trap into HS mode, from virt */
 936                 riscv_cpu_swap_hypervisor_regs(env);
 937                 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
 938                                          env->priv);
 939                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
 940                                          riscv_cpu_virt_enabled(env));
 941
 942                 htval = env->guest_phys_fault_addr;
 943
 944                 riscv_cpu_set_virt_enabled(env, 0);
 945                 riscv_cpu_set_force_hs_excep(env, 0);
 946             } else {
 947                 /* Trap into HS mode */
 948                 if (!two_stage_lookup) {
 949                     env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
 950                                              riscv_cpu_virt_enabled(env));
 951                 }
 952                 htval = env->guest_phys_fault_addr;
 953             }
 954         }
 955
 956         s = env->mstatus;
 957         s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 958         s = set_field(s, MSTATUS_SPP, env->priv);
 959         s = set_field(s, MSTATUS_SIE, 0);
 960         env->mstatus = s;
 961         env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
 962         env->sepc = env->pc;
 963         env->sbadaddr = tval;
 964         env->htval = htval;
 965         env->pc = (env->stvec >> 2 << 2) +
 966             ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
 967         riscv_cpu_set_mode(env, PRV_S);
 968     } else {
 969         /* handle the trap in M-mode */
 970         if (riscv_has_ext(env, RVH)) {
 971             if (riscv_cpu_virt_enabled(env)) {
 972                 riscv_cpu_swap_hypervisor_regs(env);
 973             }
 974             env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
 975                                      riscv_cpu_virt_enabled(env));
 976             if (riscv_cpu_virt_enabled(env) && tval) {
 977                 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
 978             }
 979
 980             mtval2 = env->guest_phys_fault_addr;
 981
 982             /* Trapping to M mode, virt is disabled */
 983             riscv_cpu_set_virt_enabled(env, 0);
 984             riscv_cpu_set_force_hs_excep(env, 0);
 985         }
 986
 987         s = env->mstatus;
 988         s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 989         s = set_field(s, MSTATUS_MPP, env->priv);
 990         s = set_field(s, MSTATUS_MIE, 0);
 991         env->mstatus = s;
 992         env->mcause = cause | ~(((target_ulong)-1) >> async);
 993         env->mepc = env->pc;
 994         env->mbadaddr = tval;
 995         env->mtval2 = mtval2;
 996         env->pc = (env->mtvec >> 2 << 2) +
 997             ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
 998         riscv_cpu_set_mode(env, PRV_M);
 999     }
1000
1001     /* NOTE: it is not necessary to yield load reservations here. It is only
1002      * necessary for an SC from "another hart" to cause a load reservation
1003      * to be yielded. Refer to the memory consistency model section of the
1004      * RISC-V ISA Specification.
1005      */
1006
1007 #endif
1008     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
1009 }