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target/riscv: rvv-1.0: implement vstart CSR
2021-12-20 Frank Changtarget/riscv: rvv-1.0: implement vstart CSR
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing floating-point/integer...
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2021-12-20 Frank Changtarget/riscv: add "set round to odd" rounding mode...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point/integer...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point/integer type...
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2021-12-20 Frank Changtarget/riscv: introduce floating-point rounding mode...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point min/max instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove integer extract instruction
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove vmford.vv and vmford.vf
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove widening saturating scaled...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width scaling shift instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point reduction...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width floating-point...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing fixed-point clip instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point slide instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: slide instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: mask-register logical instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point compare instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer comparison instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width saturating add...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening integer multiply-add...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing integer right shift...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer add-with-carry/subtract...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width bit shift instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width averaging add and...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer extension instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: whole register move instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point scalar move instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point move instruction
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer scalar move instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: register gather instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: allow load element with sign...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: element index instruction
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: iota instruction
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: set-X-first mask bit instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: find-first-set mask bit instruction
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: count population in mask instruction
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point classify instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point square-root instruction
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: take fractional LMUL into vector...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: update vext_max_elems() for...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: load/store whole register instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: fault-only-first unit stride...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: fix address index overflow bug...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: index load and store instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: stride load and store instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: configure instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove amo operations instructions
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2021-12-20 Frank Changtarget/riscv: rvv:1.0: add translation-time nan-box...
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2021-12-20 Frank Changtarget/riscv: introduce more imm value modes in translator...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: update check functions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add VMA and VTA
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add fractional LMUL
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove MLEN calculations
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: check MSTATUS_VS when accessing...
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2021-12-20 Greentime Hutarget/riscv: rvv-1.0: add vlenb register
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add vcsr register
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove rvv related codes from...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add translation-time vector...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: introduce writable misa.v field
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add sstatus VS field
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: set mstatus.SD bit if mstatus...
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add mstatus VS field
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2021-12-20 Frank Changtarget/riscv: Use FIELD_EX32() to extract wd field
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2021-12-20 Frank Changtarget/riscv: drop vector 0.7.1 and add 1.0 support
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2021-12-20 Frank Changtarget/riscv: zfh: add Zfhmin cpu property
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2021-12-20 Frank Changtarget/riscv: zfh: implement zfhmin extension
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2021-12-20 Frank Changtarget/riscv: zfh: add Zfh cpu property
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision floating-point classify
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision floating-point compare
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision convert and move
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision computational
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision load and store
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2021-11-22 Philippe Mathieu... hw/misc/sifive_u_otp: Do not reset OTP content on hardware...
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2021-11-22 Thomas Huthhw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device...
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2021-11-17 Richard Hendersonmeson.build: Merge riscv32 and riscv64 cpu family
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2021-11-17 Bin Mengtarget/riscv: machine: Sort the .subsections
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2021-10-29 Chih-Min Chaotarget/riscv: change the api for RVF/RVD fmin/fmax
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2021-10-29 Chih-Min Chaosoftfloat: add APIs to handle alternative sNaN propagation...
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2021-10-28 Alexey Baturotarget/riscv: Allow experimental J-ext to be turned on
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2021-10-28 Anatoly Parshintsevtarget/riscv: Implement address masking functions required...
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2021-10-28 Alexey Baturotarget/riscv: Support pointer masking for RISC-V for...
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2021-10-28 Alexey Baturotarget/riscv: Print new PM CSRs in QEMU logs
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2021-10-28 Alexey Baturotarget/riscv: Add J extension state description
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2021-10-28 Alexey Baturotarget/riscv: Support CSRs required for RISC-V PM extension...
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2021-10-28 Alexey Baturotarget/riscv: Add CSR defines for RISC-V PM extension
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2021-10-28 Alexey Baturotarget/riscv: Add J-extension into RISC-V
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2021-10-28 Alistair Francishw/riscv: opentitan: Fixup the PLIC context addresses
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2021-10-28 Alistair Francishw/riscv: virt: Use the PLIC config helper function
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2021-10-28 Alistair Francishw/riscv: microchip_pfsoc: Use the PLIC config helper...
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2021-10-28 Alistair Francishw/riscv: sifive_u: Use the PLIC config helper function
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2021-10-28 Alistair Francishw/riscv: boot: Add a PLIC config string function
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2021-10-28 Alistair Francishw/riscv: virt: Don't use a macro for the PLIC configuration
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2021-10-22 Bin Menghw/riscv: spike: Use MachineState::ram and MachineClass...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Bin Menghw/riscv: sifive_u: Use MachineState::ram and MachineClass...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Bin Menghw/riscv: sifive_e: Use MachineState::ram and MachineClass...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Bin Menghw/riscv: shakti_c: Use MachineState::ram and MachineClass...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Bin Menghw/riscv: opentitan: Use MachineState::ram and MachineClass...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Bin Menghw/riscv: microchip_pfsoc: Use MachineState::ram and...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU