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RISC-V: Simplify riscv_cpu_local_irqs_pending
2018-09-04 Michael ClarkRISC-V: Simplify riscv_cpu_local_irqs_pending
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-09-04 Michael ClarkRISC-V: Use atomic_cmpxchg to update PLIC bitmaps
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-09-04 Michael ClarkRISC-V: Improve page table walker spec compliance
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-09-04 Michael ClarkRISC-V: Update address bits to support sv39 and sv48
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2018-05-05 Michael ClarkRISC-V: Mark ROM read-only after copying in code
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: No traps on writes to misa,minstret,mcycle
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Make mtvec/stvec ignore vectored traps
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Add mcycle/minstret support for -icount auto
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Allow S-mode mxr access when priv ISA >= v1.10
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Clear mtval/stval on exceptions without info
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Hardwire satp to 0 for no-mmu case
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Update E and I extension order
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Remove erroneous comment from translate.c
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Remove EM_RISCV ELF_MACHINE indirection
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Make virt header comment title consistent
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Make some header guards more specific
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Fix missing break statement in disassembler
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Include instruction hex in disassembly
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Remove unused class definitions
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Remove identity_translate from load_elf
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Use ROM base address and size from memmap
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Make virt board description match spike
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-05-05 Michael ClarkRISC-V: Replace hardcoded constants with enum values
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-29 Michael ClarkRISC-V: Workaround for critical mstatus.FS bug
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-28 Michael ClarkRISC-V: Fix incorrect disassembly for addiw
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-28 Michael ClarkRISC-V: Convert cpu definition to future model
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-20 Michael ClarkRISC-V: Fix riscv_isa_string memory size bug
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V Build Infrastructure
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkSiFive Freedom U Series RISC-V Machine
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkSiFive Freedom E Series RISC-V Machine
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkSiFive RISC-V PRCI Block
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkSiFive RISC-V UART Device
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V VirtIO Machine
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkSiFive RISC-V Test Finisher
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V Spike Machines
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkSiFive RISC-V PLIC Block
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkSiFive RISC-V CLINT Block
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V HART Array
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V HTIF Console
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkAdd symbol table callback interface to load_elf
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V Linux User Emulation
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V Physical Memory Protection
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V TCG Code Generation
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V GDB Stub
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V FPU Support
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V CPU Helpers
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V Disassembler
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V CPU Core Definition
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V ELF Machine Definition
Signed-off-by: Michael Clark <mjc@sifive.com>
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2018-03-06 Michael ClarkRISC-V Maintainers
Signed-off-by: Michael Clark <mjc@sifive.com>
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AR7 emulation for QEMU