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riscv: sifive: Implement a model for SiFive FU540 OTP
2019-06-27
Michael
C
lark
disas/r
i
scv: Disassembl
e
reser
v
ed co
m
p
ressed encodings
.
.
.
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-06-24
Michael Clark
targ
e
t/riscv:
Im
p
leme
n
t riscv_cpu_unassigned_acc
e
ss
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-03-19
Mich
a
el
Cl
a
rk
RISC-V: Update
l
oad rese
r
vation c
o
mm
e
n
t
i
n
d
o
_
i
n
terrupt
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-03-19
Mic
h
ael Clark
RIS
C
-V:
C
o
nv
e
r
t trap debuggin
g
to trace events
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-03-19
Mi
c
hael Clark
R
I
S
C-V: Add sup
p
o
r
t f
o
r ve
c
tored i
n
terrupt
s
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-03-19
Michael C
l
a
rk
RISC-V: Change
loc
a
l interrupts from edge to level
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-03-19
Michae
l
C
l
a
r
k
elf: A
d
d RISC-V PSABI E
L
F header defines
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-03-19
Mic
h
ael Clark
RISC-V: Remov
e
unn
e
ce
s
sary disasse
m
bler constraints
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-03-19
M
i
chael Clark
R
ISC-
V
:
A
llo
w
in
t
errupt controllers to cla
i
m interru
p
ts
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-03-19
Michael Clark
R
I
S
C-V
:
Replace __builtin
_
popcount
w
ith
ctp
o
p8 in
PLIC
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-02-11
Micha
e
l Clark
RIS
C
-V:
A
d
d misa runtime
write s
u
pport
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-02-11
M
i
c
hael Clark
RISC-V: Add
m
isa
.
MAFD ch
e
c
k
s
to
translate
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-02-11
Michael Clark
RISC-
V
: Ad
d
misa to Dis
a
s
Context
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-02-11
Michael Clark
RISC-V: Use riscv prefix consistently on cpu h
e
lpers
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-02-11
Mi
c
hael Clark
RISC-V: Implement mstatus
.
TSR/TW/TVM
Signed-off-by:
Michael Clark
<mjc@sifive.com>
Co-authored-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-01-09
Michael Cl
a
rk
RISC-V: Implement ex
i
ste
n
t
i
al
predicates
for CSRs
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-01-09
M
i
cha
e
l Clark
R
I
SC-V:
I
mpleme
n
t
a
tomic mip
/
s
i
p CSR updates
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-01-08
Mic
h
ael Clar
k
RISC-V: Implement modular C
S
R helper interface
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-12-20
M
i
chael Clark
RISC-V: Enable second UART
on
s
ifiv
e
_e an
d
s
ifive_u
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-12-20
Mich
a
el
C
lark
RISC-V: Fix PLIC pending bitfield reads
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-12-20
M
ichael Clark
RISC-V: Fi
x
CL
I
NT timecmp low 32-bit writes
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-12-20
M
i
cha
e
l Clark
R
ISC-
V
:
Add ha
r
tid and \n to
in
t
errupt lo
g
g
i
ng
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-10-17
Michael C
l
ark
RISC-V: Don't add NULL bootargs to device-tree
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-10-17
Micha
e
l Clark
RISC-V: A
d
d mis
s
ing
f
ree
f
or plic
_
hart_confi
g
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-10-17
Michael Clark
RIS
C
-V: Update C
S
R and
int
e
rrupt def
i
nitions
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-10-17
Michael
Clark
RI
S
C
-
V:
Move non
-
ops from op_
h
el
p
er
to cpu_helper
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-10-17
Micha
e
l
Cl
a
rk
RISC-V: Allow se
t
ti
n
g
a
n
d clearing m
u
lt
i
ple irqs
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-09-04
Mic
h
ael
C
l
a
rk
RISC-V:
Simpli
f
y riscv_cpu_local_irqs_pendi
n
g
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-09-04
Michael Clark
RISC-V:
Use a
t
omic_cmpxchg to
u
pda
t
e P
L
IC bitmaps
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-09-04
M
i
c
hael Clark
RI
S
C
-
V:
I
mprove page table walker spec compliance
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-09-04
Michael Clark
RISC-V: Update ad
d
re
s
s bits to
support sv3
9
a
n
d
s
v48
commit
|
commitdiff
|
tree
2018-05-05
Micha
e
l Clark
RISC-V
:
M
ark R
O
M
r
e
a
d-only
a
fter co
p
ying in code
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mi
c
h
ael C
l
ar
k
RISC-V:
No tra
p
s on wr
i
t
es
t
o m
i
sa,min
s
t
r
et,mcycl
e
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael C
l
ark
RISC
-
V: M
a
ke
m
tvec/stve
c
ignore ve
c
tored
traps
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mich
a
el Cla
r
k
R
I
S
C
-V:
A
dd mcyc
l
e/minst
r
et supp
o
rt for -icount
a
u
t
o
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RISC-V: Us
e
[
m
s
]
counteren CSRs when priv
I
SA >= v1
.
10
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mich
a
e
l Cla
r
k
RISC-V: Allow
S-
m
ode mx
r
a
ccess when priv ISA >=
v
1
.
10
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mic
h
ae
l
Clark
RISC-V: Clear mtval/stval
on e
x
ceptions witho
u
t info
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mic
h
ael Clark
RISC-V: Hardw
i
re sa
t
p to 0
f
o
r no-mmu case
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Cla
r
k
RISC-V: Upda
t
e E and I extension order
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
i
chael C
l
ark
RISC-V: Remove
e
rron
e
ous com
m
e
n
t fr
o
m
tr
a
n
slate
.
c
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clar
k
RI
S
C
-
V
: R
e
move EM_RISCV ELF_MACHINE indirection
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael
Clark
RISC-V:
Make v
i
r
t
he
a
d
er comment t
i
tle consisten
t
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clar
k
RISC-V: Make som
e
heade
r
guards
m
o
r
e specific
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RIS
C
-V: Fix missing bre
a
k
st
a
tement in disa
s
s
e
m
bler
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RISC-V:
I
n
clu
d
e instruction
hex in disassembly
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael
Clark
R
I
S
C
-
V
:
Remove unused class definitions
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael
Clar
k
R
I
S
C-V: Remove iden
t
ity_
t
ranslate from load_
e
lf
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
R
I
SC
-
V: Use ROM base addr
e
ss and size fr
o
m memmap
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mi
c
hael Cl
a
rk
RISC-V: Make virt
b
oard descriptio
n
m
atch spike
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michae
l
Clark
RISC-V:
Repl
a
ce hardcoded co
n
stants w
i
th enum values
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-29
Mi
c
hael Clark
RISC-V: Workaround for cri
t
ical mstatus
.
FS bug
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-28
M
ichael
Clark
RISC-V:
Fix in
c
orrect disassembly for a
d
diw
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-28
Michael Clark
RISC-V: Conver
t
c
p
u def
i
nition to fu
t
ure m
o
del
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-20
Mic
h
a
el
C
lark
RISC-V: Fix riscv_
i
sa
_
string
memo
r
y size bug
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael C
l
ark
RISC-V Build Infrastructure
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael C
l
ark
S
i
Five Freedom U Series RI
S
C-V Machine
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
SiFive
F
reedom
E
S
eries
RIS
C
-V Machine
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michae
l
Clark
SiFive
R
ISC-V PRC
I
Block
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
lark
SiFiv
e
RI
S
C-V UART Device
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
ic
h
ael C
l
ark
R
I
SC-V VirtI
O
Machi
n
e
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l Clark
SiFive RISC-V Test Finisher
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l Clark
RISC-V
Spike Machines
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l
C
lark
SiFive RISC-
V
PLIC B
l
o
c
k
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
SiFive RIS
C
-V CLINT
B
lock
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mich
a
el Clark
R
ISC-V HART A
r
ray
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
RIS
C
-V HTIF
Consol
e
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
ichael Cl
a
r
k
Add symbol ta
b
le c
a
llback in
t
erface to load
_
elf
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
h
a
el Clark
RISC-V Lin
u
x User Emu
l
a
t
i
o
n
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
ichae
l
Clark
RISC-V
Physical Memory
Protection
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
R
ISC-V TCG Code
Ge
n
era
t
ion
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
hae
l
Clark
R
ISC-V G
D
B Stub
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
lark
R
I
S
C
-
V FPU Support
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
Cla
r
k
RISC-V C
P
U
Helpers
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
ha
e
l Clark
RISC-V Disassemb
l
er
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
i
chael
C
lark
RI
S
C-V
C
P
U
Core
D
efinit
i
on
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clar
k
RISC-V ELF Ma
c
hin
e
D
e
fini
t
i
on
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
l
a
rk
RISC-V
M
aintainers
Add
Michael Clark
, Palmer Dabbelt, Sagar Karandikar...
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree