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target/riscv: Consolidate RV32/64 16-bit instructions
2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 16-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 32-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove an unused CASE_OP_32_64 macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the unused HSTATUS_WPRI macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded MSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded HGATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded RVXLEN macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Emmanuel Blottarget/riscv: fix a typo with interrupt names
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Frank Changfpu/softfloat: set invalid excp flag for RISC-V muladd...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alexander Wagnerhw/riscv: Fix OT IBEX reset vector
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Emmanuel Blottarget/riscv: fix exception index on instruction access...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Frank Changtarget/riscv: fix vrgather macro index variable type bug
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Add ePMP support for the Ibex CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv/pmp: Remove outdated comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Hou Weiyingtarget/riscv: Add a config option for ePMP
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Hou Weiyingtarget/riscv: Implementation of enhanced PMP (ePMP)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Hou Weiyingtarget/riscv: Add ePMP CSR access functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Add the ePMP feature
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Hou Weiyingtarget/riscv: Define ePMP mseccfg
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix the PMP is locked check when using TOR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Kdocs: Add documentation for shakti_c machine
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 LIU Zhiweitarget/riscv: Fixup saturate subtract function
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Jade Finkriscv: don't look at SUM when accessing memory from...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francishw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francishw/opentitan: Update the interrupt layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair FrancisMAINTAINERS: Update the RISC-V CPU Maintainers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Use RISCVException enum for CSR access
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix 32-bit HS mode access permissions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR predicates
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Convert the RISC-V exceptions to an enum
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Khw/riscv: Connect Shakti UART to Shakti platform
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Khw/char: Add Shakti UART emulation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Kriscv: Add initial support for Shakti C machine
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Ktarget/riscv: Add Shakti C class CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Bin Menghw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Dylan Jhongtarget/riscv: Align the data type of reset vector address
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Axel Heiderdocs/system/generic-loader.rst: Fix style
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Atish Patratarget/riscv: Remove privilege v1.9 specific CSR related...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Prevent lost illegal instruction exceptions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Bin Mengdocs/system: riscv: Add documentation for 'microchip...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Bin Menghw/riscv: microchip_pfsoc: Map EMMC/SD mux register
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Bin Menghw/block: m25p80: Support fast read for SST flashes
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Add proper two-stage lookup exception...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Fix read and write accesses to vsip and...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Asherah Connorhw/riscv: allow ramfb on virt
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Asherah Connorhw/riscv: Add fw_cfg support to virt
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Use background registers also for MSTATUS_MPV
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Make VSTIP and VSEIP read-only in hip
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Adjust privilege level for HLV(X)/HSV...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Jim Shutarget/riscv: flush TLB pages if PMP permission has...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Jim Shutarget/riscv: add log of PMP permission checking
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Jim Shutarget/riscv: propagate PMP permission to TLB page
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Alexander Wagnerhw/char: disable ibex uart receive if the buffer is...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Frank Changtarget/riscv: fix vs() to return proper error code
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: virt: Map high mmio for PCIe
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: virt: Limit RAM size in a 32-bit system
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: Drop 'struct MemmapEntry'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Alistair FrancisMAINTAINERS: Add a SiFive machine section
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Laurent Viviergoldfish_rtc: re-arm the alarm after migration
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Mengdocs/system: riscv: Add documentation for sifive_u...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Mengdocs/system: Add RISC-V documentation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Mengdocs/system: Sort targets in alphabetical order
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: sifive_u: Add QSPI2 controller and connect...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: sifive_u: Add QSPI0 controller and connect...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/ssi: Add SiFive SPI controller support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/block: m25p80: Add various ISSI flash information
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/block: m25p80: Add ISSI SPI flash support
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Yifei Jiangtarget-riscv: support QMP dump-guest-memory
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Mengroms/opensbi: Upgrade from v0.8 to v0.9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/misc: sifive_u_otp: Use error_report() when block...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Mengtarget/riscv: Declare csr_ops[] with a known size
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Alistair Francisriscv: Pass RISCVHartArrayState by pointer
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Bin Mengtarget/riscv: Remove built-in GDB XML files for CSRs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Bin Mengtarget/riscv: Generate the GDB XML file for CSR registers...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Bin Mengtarget/riscv: Add CSR name in the CSR function table
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Bin Mengtarget/riscv: Make csr_ops[CSR_TABLE_SIZE] external
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Green Wanhw/misc/sifive_u_otp: handling the fails of blk_pread...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Bin Menghw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Atish Patratarget/riscv/pmp: Raise exception if no PMP entry is...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Atish PatraRISC-V: Place DTB at 3GB boundary instead of 4GB
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Sylvain Pelissiergdb: riscv: Add target description
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Xuzhou Chenghw/block: m25p80: Implement AAI-WP command support...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Bin Menghw/block: m25p80: Don't write to flash if write is...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francisriscv/opentitan: Update the OpenTitan memory layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francishw/riscv: Use the CPU to determine if 32-bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: cpu: Set XLEN independently from target
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: csr: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: cpu_helper: Remove compile time XLEN...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: cpu: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: Specify the XLEN for CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: Add a riscv_cpu_is_32bit() helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: fpu_helper: Match function defs in HELPER...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francishw/riscv: sifive_u: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francishw/riscv: spike: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francishw/riscv: virt: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU