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2022-04-29	Alistair Francis	hw/riscv: virt: Add support for generating platform... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-04-29	Alistair Francis	hw/riscv: virt: Create a platform bus Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-04-29	Alistair Francis	hw/core: Move the ARM sysbus-fdt to core Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-04-29	Alistair Francis	hw/riscv: virt: Add a machine done notifier Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-04-22	Alistair Francis	target/riscv: Allow software access to MIP SEIP Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-04-22	Alistair Francis	target/riscv: cpu: Fixup indentation Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	target/riscv: Implement the stval/mtval illegal instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	target/riscv: Fixup setting GVA Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	target/riscv: Set the opcode in DisasContext Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	hw/riscv: virt: Allow support for 32 cores Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	hw/riscv: Use error_fatal for SoC realisation Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	target/riscv: Enable the Hypervisor extension by default Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	target/riscv: Mark the Hypervisor extension as non... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	hw/intc: sifive_plic: Cleanup remaining functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	hw/intc: sifive_plic: Cleanup the read function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	hw/intc: sifive_plic: Cleanup the write function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2022-01-08	Alistair Francis	hw/intc: sifive_plic: Add a reset function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-28	Alistair Francis	hw/riscv: opentitan: Fixup the PLIC context addresses Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-28	Alistair Francis	hw/riscv: virt: Use the PLIC config helper function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-28	Alistair Francis	hw/riscv: microchip_pfsoc: Use the PLIC config helper... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-28	Alistair Francis	hw/riscv: sifive_u: Use the PLIC config helper function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-28	Alistair Francis	hw/riscv: boot: Add a PLIC config string function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-28	Alistair Francis	hw/riscv: virt: Don't use a macro for the PLIC configuration Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-22	Alistair Francis	hw/intc: sifive_plic: Cleanup the irq_request function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-22	Alistair Francis	hw/intc: sifive_plic: Cleanup the realize function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-22	Alistair Francis	hw/intc: sifive_plic: Move the properties Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-22	Alistair Francis	hw/intc: Remove the Ibex PLIC Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-22	Alistair Francis	hw/riscv: opentitan: Update to the latest build Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-21	Alistair Francis	target/riscv: Organise the CPU properties Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-21	Alistair Francis	target/riscv: Remove some unused macros Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-10-06	Alistair Francis	hw/riscv: shakti_c: Mark as not user creatable Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-09-21	Alistair Francis	hw/riscv: opentitan: Correct the USB Dev address Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-09-20	Alistair Francis	sifive_u: Connect the SiFive PWM device Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-09-20	Alistair Francis	hw/timer: Add SiFive PWM support Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-09-20	Alistair Francis	hw/intc: ibex_timer: Convert the timer to use RISC... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-09-20	Alistair Francis	hw/intc: sifive_plic: Convert the PLIC to use RISC... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-09-20	Alistair Francis	hw/intc: ibex_plic: Convert the PLIC to use RISC-V... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-09-20	Alistair Francis	hw/intc: sifive_clint: Use RISC-V CPU GPIO lines Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-09-20	Alistair Francis	target/riscv: Expose interrupt pending bits as GPIO... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-09-20	Alistair Francis	target/riscv: Update the ePMP CSR address Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-07-14	Alistair Francis	hw/riscv/boot: Check the error of fdt_pack() Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-07-14	Alistair Francis	hw/riscv: opentitan: Add the flash alias Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-07-14	Alistair Francis	hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-07-14	Alistair Francis	char: ibex_uart: Update the register layout Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-06-24	Alistair Francis	hw/riscv: OpenTitan: Connect the mtime and mtimecmp... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-06-24	Alistair Francis	hw/timer: Initial commit of Ibex Timer Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-06-24	Alistair Francis	hw/char/ibex_uart: Make the register layout private Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-06-24	Alistair Francis	target/riscv: Use target_ulong for the DisasContext... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-06-07	Alistair Francis	target/riscv/pmp: Add assert for ePMP operations Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-06-07	Alistair Francis	docs/system: Move the RISC-V -bios information to removed Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Fix the RV64H decode comment Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Consolidate RV32/64 16-bit instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Consolidate RV32/64 32-bit instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Remove an unused CASE_OP_32_64 macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Remove the unused HSTATUS_WPRI macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Remove the hardcoded SATP_MODE macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Remove the hardcoded MSTATUS_SD macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Remove the hardcoded HGATP_MODE macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Remove the hardcoded SSTATUS_SD macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Remove the hardcoded RVXLEN macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Add ePMP support for the Ibex CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv/pmp: Remove outdated comment Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Add the ePMP feature Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Fix the PMP is locked check when using TOR Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	hw/opentitan: Update the interrupt layout Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	MAINTAINERS: Update the RISC-V CPU Maintainers Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Use RISCVException enum for CSR access Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Use the RISCVException enum for CSR operations Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Fix 32-bit HS mode access permissions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Use the RISCVException enum for CSR predicates Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-05-11	Alistair Francis	target/riscv: Convert the RISC-V exceptions to an enum Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-03-04	Alistair Francis	MAINTAINERS: Add a SiFive machine section Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-02-13	Alistair Francis	linux-user/signal: Decode waitid si_code Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2021-01-16	Alistair Francis	riscv: Pass RISCVHartArrayState by pointer Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	riscv/opentitan: Update the OpenTitan memory layout Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	hw/riscv: Use the CPU to determine if 32-bit Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	target/riscv: cpu: Set XLEN independently from target Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	target/riscv: csr: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	target/riscv: cpu_helper: Remove compile time XLEN... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	target/riscv: cpu: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	target/riscv: Specify the XLEN for CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	target/riscv: Add a riscv_cpu_is_32bit() helper function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	target/riscv: fpu_helper: Match function defs in HELPER... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	hw/riscv: sifive_u: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	hw/riscv: spike: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	hw/riscv: virt: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	hw/riscv: boot: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	riscv: virt: Remove target macro conditionals Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	riscv: spike: Remove target macro conditionals Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	hw/riscv: Expand the is 32-bit check to support more... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-12-18	Alistair Francis	intc/ibex_plic: Clear interrupts that occur during... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-11-17	Alistair Francis	register: Remove unnecessary NULL check Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-11-14	Alistair Francis	intc/ibex_plic: Ensure we don't loose interrupts Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-11-14	Alistair Francis	intc/ibex_plic: Fix some typos in the comments Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-11-09	Alistair Francis	hw/intc/ibex_plic: Clear the claim register when read Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-11-09	Alistair Francis	target/riscv: Split the Hypervisor execute load helpers Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-11-09	Alistair Francis	target/riscv: Remove the hyp load and store functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-11-09	Alistair Francis	target/riscv: Remove the HS_TWO_STAGE flag Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
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AR7 emulation for QEMU

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