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hw/riscv: virt: Create a platform bus
2022-04-29 Alistair Francishw/riscv: virt: Create a platform bus
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/core: Move the ARM sysbus-fdt to core
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/riscv: virt: Add a machine done notifier
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Alistair Francistarget/riscv: Allow software access to MIP SEIP
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Alistair Francistarget/riscv: cpu: Fixup indentation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Implement the stval/mtval illegal instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Fixup setting GVA
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Set the opcode in DisasContext
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/riscv: virt: Allow support for 32 cores
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/riscv: Use error_fatal for SoC realisation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Enable the Hypervisor extension by default
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Mark the Hypervisor extension as non...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup remaining functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup the read function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup the write function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Add a reset function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: opentitan: Fixup the PLIC context addresses
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: virt: Use the PLIC config helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: microchip_pfsoc: Use the PLIC config helper...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: sifive_u: Use the PLIC config helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: boot: Add a PLIC config string function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: virt: Don't use a macro for the PLIC configuration
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Alistair Francishw/intc: sifive_plic: Cleanup the irq_request function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ba35f754dcca7fdd9f08d6.1634524691.git.alistair.francis@wdc.com
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2021-10-22 Alistair Francishw/intc: sifive_plic: Cleanup the realize function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
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2021-10-22 Alistair Francishw/intc: sifive_plic: Move the properties
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...82bf8b197535ccd1996939.1634524691.git.alistair.francis@wdc.com
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2021-10-22 Alistair Francishw/intc: Remove the Ibex PLIC
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...1b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
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2021-10-22 Alistair Francishw/riscv: opentitan: Update to the latest build
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
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2021-10-21 Alistair Francistarget/riscv: Organise the CPU properties
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...02be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com
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2021-10-21 Alistair Francistarget/riscv: Remove some unused macros
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...d44c1e371c5c99cc2fa15a.1634531504.git.alistair.francis@wdc.com
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2021-10-06 Alistair Francishw/riscv: shakti_c: Mark as not user creatable
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...427b47a1b1d5ab475a2edd.1632871759.git.alistair.francis@wdc.com>
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2021-09-21 Alistair Francishw/riscv: opentitan: Correct the USB Dev address
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...17d7075b750ece3acb1535.1631767043.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francissifive_u: Connect the SiFive PWM device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...29a56f5ca60b0b27852a4d.1631159656.git.alistair.francis@wdc.com
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2021-09-20 Alistair Francishw/timer: Add SiFive PWM support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a6ad311ab892ac69134d8b.1631159656.git.alistair.francis@wdc.com
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2021-09-20 Alistair Francishw/intc: ibex_timer: Convert the timer to use RISC...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
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2021-09-20 Alistair Francishw/intc: sifive_plic: Convert the PLIC to use RISC...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...45c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com
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2021-09-20 Alistair Francishw/intc: ibex_plic: Convert the PLIC to use RISC-V...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...5f0c37ab35b253371027a8.1630301632.git.alistair.francis@wdc.com
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2021-09-20 Alistair Francishw/intc: sifive_clint: Use RISC-V CPU GPIO lines
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c7ddad84c146de62a56736.1630301632.git.alistair.francis@wdc.com
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2021-09-20 Alistair Francistarget/riscv: Expose interrupt pending bits as GPIO...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...5a44e73f6442b11c703c53.1630301632.git.alistair.francis@wdc.com
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2021-09-20 Alistair Francistarget/riscv: Update the ePMP CSR address
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0e63d113885c98586053f3.1630543194.git.alistair.francis@wdc.com
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2021-07-14 Alistair Francishw/riscv/boot: Check the error of fdt_pack()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9f76094e4bc5296e0643b9.1626303527.git.alistair.francis@wdc.com
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2021-07-14 Alistair Francishw/riscv: opentitan: Add the flash alias
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com
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2021-07-14 Alistair Francishw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...6a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com
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2021-07-14 Alistair Francischar: ibex_uart: Update the register layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com
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2021-06-24 Alistair Francishw/riscv: OpenTitan: Connect the mtime and mtimecmp...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...b8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
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2021-06-24 Alistair Francishw/timer: Initial commit of Ibex Timer
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com
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2021-06-24 Alistair Francishw/char/ibex_uart: Make the register layout private
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0387a3ba2fad7d116a4986.1624001156.git.alistair.francis@wdc.com
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2021-06-24 Alistair Francistarget/riscv: Use target_ulong for the DisasContext...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e3eec320b6a683ab56f705.1622435221.git.alistair.francis@wdc.com
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2021-06-07 Alistair Francistarget/riscv/pmp: Add assert for ePMP operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...8c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
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2021-06-07 Alistair Francisdocs/system: Move the RISC-V -bios information to removed
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Fix the RV64H decode comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 16-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 32-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove an unused CASE_OP_32_64 macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the unused HSTATUS_WPRI macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded MSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded HGATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded RVXLEN macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Add ePMP support for the Ibex CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv/pmp: Remove outdated comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9a78fdba85280cab4dd27f.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Add the ePMP feature
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c3ae009f5467e2b3960ce0.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Fix the PMP is locked check when using TOR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francishw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francishw/opentitan: Update the interrupt layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...10da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
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2021-05-11 Alistair FrancisMAINTAINERS: Update the RISC-V CPU Maintainers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Use RISCVException enum for CSR access
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Fix 32-bit HS mode access permissions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR predicates
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Convert the RISC-V exceptions to an enum
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
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2021-03-04 Alistair FrancisMAINTAINERS: Add a SiFive machine section
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...adf81ae194718f2f17c402.1612836645.git.alistair.francis@wdc.com
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2021-02-13 Alistair Francislinux-user/signal: Decode waitid si_code
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3e638abe9e2d78c09a3d5b.1611080607.git.alistair.francis@wdc.com>
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2021-01-16 Alistair Francisriscv: Pass RISCVHartArrayState by pointer
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...69991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisriscv/opentitan: Update the OpenTitan memory layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: Use the CPU to determine if 32-bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...7788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: cpu: Set XLEN independently from target
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: csr: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: cpu_helper: Remove compile time XLEN...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...55d677e911b9432eb8f340.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: cpu: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...90066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: Specify the XLEN for CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...fbeb0194293bd24d65f5dc.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: Add a riscv_cpu_is_32bit() helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...35b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: fpu_helper: Match function defs in HELPER...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...73a647b8aac7e023cba145.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: sifive_u: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: spike: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e421a0fcd9ac8a92014607.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: virt: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: boot: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisriscv: virt: Remove target macro conditionals
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisriscv: spike: Remove target macro conditionals
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...6a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: Expand the is 32-bit check to support more...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisintc/ibex_plic: Clear interrupts that occur during...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9123cc8a7837af8fa071cf.1607100423.git.alistair.francis@wdc.com
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2020-11-17 Alistair Francisregister: Remove unnecessary NULL check
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-14 Alistair Francisintc/ibex_plic: Ensure we don't loose interrupts
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...828e7c3f85293a09a65b12.1605136387.git.alistair.francis@wdc.com
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2020-11-14 Alistair Francisintc/ibex_plic: Fix some typos in the comments
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...67ac909926368d1bcb7cf5.1605136387.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francishw/intc/ibex_plic: Clear the claim register when read
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...747f3bda193fcf43af4558.1604629928.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Split the Hypervisor execute load helpers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...77f3c1ae811dea98ab9e36.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Remove the hyp load and store functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...d18aad7074c6649f17de2c.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Remove the HS_TWO_STAGE flag
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...85f914cee18f905007a922.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Set the virtualised MMU mode when doing...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...53f13cac2fb86dc91ebee8.1604464950.git.alistair.francis@wdc.com
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AR7 emulation for QEMU