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hw/riscv: virt: Create a platform bus
2022-02-16
L
IU Zhiwei
target/ris
c
v
:
Fix vill
field wri
t
e in
v
type
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhi
w
ei
target/riscv: Relax UXL fi
e
ld
f
or
debugging
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
target/
r
iscv: Enable uxl field write
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LI
U
Z
h
i
wei
t
a
rget/riscv:
Set default XLEN
f
or hypervi
s
or
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
t
a
rget/riscv: Ad
j
ust
s
calar reg in vec
t
o
r
with
X
L
EN
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
L
I
U Zhiwei
t
a
r
get/ri
s
c
v: Adjust
vector address wit
h
mask
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Z
h
iwei
t
a
rget/
r
iscv:
F
ix check
r
ange fo
r
first
f
a
u
lt o
n
ly
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
L
I
U Zhiwei
target/
r
iscv:
R
emove V
I
LL fiel
d
in VTYPE
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
target/riscv: Adj
u
st
vsetvl acco
r
ding to XLEN
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
L
IU Z
h
iwei
target/riscv: Split out
t
h
e
vi
l
l
from vtype
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
target/ris
c
v: Split pm_en
a
bled into mask a
n
d
base
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
target/r
i
scv: Calc
u
l
ate a
d
dress acc
o
r
ding to XLE
N
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiw
e
i
tar
g
et
/
r
i
scv: Alloc t
c
g g
l
ob
a
l for cur_pm[ma
s
k|b
a
se]
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
target/riscv: Create c
u
rre
n
t pm fields in env
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
L
I
U Zhiwei
targe
t
/riscv: Adjust csr wr
i
t
e mas
k
with XLEN
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
ta
r
get/riscv: Re
l
ax debug c
h
eck
for pm write
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
target/riscv: Use
gdb xml a
c
c
ording to ma
x
mxlen
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
target/riscv: Exte
n
d pc for ru
n
t
i
m
e
pc write
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
target/riscv: Ignore t
h
e
pc bits above XLEN
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Z
h
i
w
ei
tar
g
et/ri
s
cv: Create xl field in env
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
L
I
U
Z
hi
w
ei
tar
g
e
t/riscv: Sign e
x
t
e
nd pc f
o
r different XLEN
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
tar
g
et/riscv: Sign e
x
tend link reg for
j
al a
n
d jalr
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU
Z
hiwei
tar
g
e
t/riscv: D
o
n't save pc when except
i
on ret
u
r
n
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2022-01-21
LIU Zhiwei
target/ris
c
v
:
A
djust p
m
pcfg
a
ccess with
m
x
l
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-12-20
LIU Zhiwei
targ
e
t/riscv: rvv-1
.
0
:
add v
c
sr regis
t
er
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-12-20
LIU Zhiwei
t
arget/ris
c
v:
rvv-1
.
0: add sstatus VS field
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-12-20
L
I
U Z
h
iwe
i
t
a
rget/riscv: rvv-1
.
0
: add
mstatus VS
fi
e
ld
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-09-20
LIU
Z
hiwei
target/riscv: Fix satp write
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-09-01
L
I
U Zhiwei
target/riscv: Add User C
S
Rs r
e
ad
-
only check
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-09-01
LIU Zhiwei
target/riscv: Don't wrongly
override isa
vers
i
o
n
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-06-29
LIU Z
h
i
w
ei
tcg
:
Implement tcg
_
gen_vec_add{
s
ub
}
32_tl
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-06-29
LIU Zhiwei
tcg: Add tcg_gen_vec_shl{shr}{sar
}
8i_i32
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-06-29
LIU Zhiwei
tcg: Add tcg_ge
n
_vec_shl{shr}
{
sar}16i_i32
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-06-29
LIU Z
h
iwei
tcg:
A
dd
t
c
g_gen_
v
ec_add{su
b
}8_i32
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-06-29
LIU Z
h
iwei
tcg: Add tcg_
g
e
n
_ve
c
_add{
s
ub}16_i32
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-06-07
LIU Zh
i
wei
target/
r
iscv: Pa
s
s th
e
sa
m
e value t
o
oprsz and maxsz
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2021-05-11
LIU Zhiwe
i
targe
t
/risc
v
: Fi
x
up sat
u
r
a
te su
b
tra
c
t
function
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-08-28
LIU Zhiwei
s
o
ft
f
loat:
D
e
fine misc operations for bfloat16
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-08-28
LIU Zhi
w
e
i
softfloat: D
e
fine
con
v
e
r
t oper
a
tion
s
for bfloat16
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-08-28
LIU Zhiwei
soft
f
loa
t
:
Defi
n
e operations
for bfloat1
6
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-08-22
LIU
Zhiwei
t
arget/riscv: check b
e
f
ore allocati
n
g
TCG temps
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-08-22
L
I
U Zhiwei
target/ris
c
v: Clean up fmv
.
w
.
x
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-22
LIU Zhiwei
target/ris
c
v: fix vector index load/store constra
i
nts
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-22
L
IU
Z
hi
w
ei
ta
r
g
et/riscv: Quiet C
o
verity com
p
lains a
b
out vamo*
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-15
LIU Zh
i
w
ei
fpu/softfloat: f
i
x
up fl
o
at16 nan recogni
t
io
n
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
L
I
U Z
h
iwei
target/riscv: confi
g
ure and turn on vector e
x
tension
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiwei
t
a
rget/riscv: vector comp
r
ess
instruction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiwe
i
target/riscv: vec
t
or register gather instr
u
ct
i
on
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU
Z
hiwei
target/riscv: v
e
ctor
s
lide instructi
o
ns
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
L
IU
Z
h
i
wei
tar
g
et/risc
v
: floating-point scalar move
i
n
s
tru
c
ti
o
ns
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhi
w
ei
ta
r
get/riscv
:
in
t
eger scalar mo
v
e
i
nstruction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
L
I
U Zhiwei
tar
g
et/ris
c
v: integer e
x
trac
t
i
n
struction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LI
U
Zhiwei
target
/
ris
c
v: vec
t
or element index instruction
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Z
h
iwei
tar
g
et/riscv: vec
t
or iota
i
nstru
c
tion
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU
Zhiwei
target/r
i
scv:
set-X
-
first ma
s
k
b
i
t
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU
Zhiwei
targ
e
t/riscv: vm
f
ir
s
t find-first
-
set mask bit
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiwei
t
a
rget/riscv
:
vector mask population
c
ount vmpopc
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU
Z
hiwei
t
arg
e
t/riscv: v
e
ct
o
r
m
ask
-
register logical inst
r
u
c
t
i
ons
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU
Zhiwei
t
arget/riscv: vector
widening
f
l
oa
t
ing-point re
d
uction
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiwei
target/riscv: vector sin
g
le-width float
i
n
g
-poin
t
re
d
uction
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiwei
t
arget/riscv: vector
w
ideing integer reduction instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiwei
target/riscv: vector si
n
gle-width
i
nteg
e
r
r
educt
i
o
n
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU
Z
hiwei
tar
g
e
t/riscv: narr
o
win
g
f
lo
a
ting-point/integ
e
r typ
e
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
L
IU Zhiwei
t
arget
/
riscv: widen
i
ng floating-point/
i
nt
e
g
er
typ
e
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhi
w
ei
target/riscv: vect
o
r f
l
oating-point/integer type-convert
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Z
h
iwei
t
a
rget/
r
iscv: vector floating-point merge instruc
t
ions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
L
I
U Zhiw
e
i
targ
e
t/risc
v
:
vector
f
l
oa
t
ing-po
i
nt c
l
assify in
s
truction
s
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiwei
targ
e
t/ris
c
v: vector
fl
o
ating-p
o
int compare i
n
s
t
ructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LI
U
Zhi
w
ei
t
arget/risc
v
:
vec
t
or fl
o
ating
-
point s
i
gn-inject
i
on
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiwei
target
/
riscv: vect
o
r
f
loating
-
point min/max instr
u
ctions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LI
U
Zhiwei
target/r
i
sc
v
: vector floating
-
poin
t
squa
r
e-
r
o
o
t ins
t
ructi
o
n
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
L
IU Zhiwei
target/riscv: vector widen
i
ng floating-po
i
n
t fused
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiwei
target/ri
s
cv
:
vector single-widt
h
floati
n
g-point fused
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
L
IU Zhiwei
target/riscv: vec
t
o
r
widening float
i
ng
-
point multiply
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiw
e
i
target/
r
iscv: vector
s
ingle-width floating-poi
n
t multi
p
ly
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
|
commitdiff
|
tree
2020-07-02
LIU Zhiw
e
i
target/riscv: vector
w
idening
f
loating-poin
t
a
dd/subtract
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
L
I
U Z
h
i
wei
targe
t
/riscv: vector single-w
i
dth
f
lo
a
t
i
n
g
-po
i
n
t
add
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
L
IU Zhiwei
targ
e
t/riscv: vector nar
r
o
w
ing
fixed-point cli
p
instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
t
arget/riscv: vector
singl
e
-
width scaling shift in
s
t
r
u
c
tions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
L
IU Zhi
w
ei
target/ris
c
v
: vector w
i
den
i
ng sat
u
r
atin
g
scal
e
d multip
l
y-ad
d
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
L
I
U
Zhi
w
ei
target/riscv: vector single-wi
d
th fractional
multiply
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Z
h
i
w
ei
target/riscv
:
vector single-widt
h
averaging add
and
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
L
I
U Zhiwei
tar
g
et/ris
c
v:
vector sing
l
e-w
i
dth saturating a
d
d an
d
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU
Zhiwei
ta
r
g
e
t
/
ri
s
cv: vector
i
nteger merge a
n
d
m
ov
e
instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
L
IU Zhiwei
tar
g
et/riscv: v
e
ctor wide
n
ing integer multiply-add
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU
Z
h
iwei
target/riscv: vec
t
or single-w
i
dth integer
m
u
l
tiply
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
t
a
rget
/
riscv:
vector wid
e
nin
g
i
n
teger multiply ins
t
r
u
c
ti
o
ns
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhi
w
e
i
target/riscv: vec
t
or integ
e
r divide in
s
truct
i
o
n
s
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU
Z
hiwe
i
target/risc
v
: ve
c
tor s
i
ngle-width in
t
eger multi
p
l
y
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
commit
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2020-07-02
LIU Zhiwei
ta
r
get/riscv: vect
o
r integer m
i
n/max
i
nst
r
u
c
tions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhi
w
e
i
target/riscv: vector integer comparis
o
n
instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zh
i
wei
ta
r
get/risc
v
: v
e
c
t
or n
a
rrow
i
n
g
intege
r
right shift
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwe
i
target/riscv: v
e
cto
r
single-
w
idth bit shift instructions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Z
h
iw
e
i
target/ri
s
cv
:
vect
o
r bitwise l
o
gical instruc
t
ions
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
t
arget/risc
v
:
v
e
c
t
o
r integ
e
r ad
d
-wi
t
h-carry / subtract
.
.
.
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LI
U
Zh
i
wei
target/riscv: vector
widening in
t
eg
e
r a
d
d and subtract
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LI
U
Zhiw
e
i
target/ris
c
v: v
e
ct
o
r single-width i
n
t
eg
e
r ad
d
and s
u
b
t
ract
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
L
I
U
Z
hi
w
ei
targ
e
t/ris
c
v
: add vector
amo o
p
erat
i
on
s
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhi
w
ei
t
arget/riscv: add fau
l
t-only-f
i
rst unit
s
tride
l
o
a
d
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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2020-07-02
LIU Zhiwei
ta
r
get
/
riscv: add vector in
d
ex
load
a
nd s
t
o
r
e
instructio
n
s
Signed-off-by:
LIU Zhiwei
<zhiwei_liu@c-sky.com>
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