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hw/riscv: virt: Create a platform bus
2022-04-29
Alist
a
ir
Francis
hw/riscv: vir
t
: C
r
eate a platform b
u
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Alis
t
air Francis
hw/c
o
r
e
: Move the
ARM sysbus-fdt to
core
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Al
i
s
t
air Fr
a
n
cis
hw/riscv: virt: Add a mach
i
ne done notifie
r
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-22
A
listair Fra
n
cis
target/riscv: Allow softwa
r
e access
to
MIP
S
EIP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-22
A
l
istair F
r
ancis
tar
g
et/riscv: cpu: Fixup
inden
t
at
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair Franc
i
s
tar
g
et/ris
c
v
: Implement the stval/mtval illegal
instruction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alis
t
air Francis
target/ris
c
v: Fix
u
p
s
etting GVA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistai
r
Francis
target/riscv
:
Set
t
h
e
op
c
ode in DisasConte
x
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alis
t
air Franc
i
s
hw/riscv:
virt: Allow support for 32
c
ores
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
A
l
i
stair Francis
h
w/riscv: Use erro
r
_fatal for
SoC rea
l
is
a
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair
F
rancis
target/riscv: Enable th
e
Hypervisor
e
xte
n
s
i
on by
d
efault
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair Francis
target/riscv: Mark the
H
ypervisor extension as non
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair Fran
c
is
hw/intc: sifive_plic: Cleanup r
e
maini
n
g function
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair
F
rancis
h
w
/i
n
tc: sif
i
ve_pl
i
c
: Cleanup t
h
e read function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistai
r
Francis
hw/intc:
s
ifive_plic:
Cleanup
the write function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alist
a
ir Francis
hw/int
c
: sifive_plic: Add a
r
eset functi
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Al
i
sta
i
r Franci
s
h
w/ri
s
c
v
: opentitan: Fixu
p
the PLI
C
cont
e
x
t
addresses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alistair Francis
h
w
/riscv: v
i
rt: Use the
PLIC config helper func
t
ion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alis
t
air F
r
ancis
h
w
/riscv:
m
i
c
rochip_pfsoc: Use the PLIC config helper
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alist
a
ir F
r
ancis
hw/riscv: sifiv
e
_u: U
s
e
the PLI
C
config help
e
r functi
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alistair Francis
hw/riscv: boot: Add a PLI
C
config string function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alist
a
i
r Francis
hw/riscv: vi
r
t: Don't u
s
e a
ma
c
ro for the PL
I
C configurati
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Alistair Francis
hw/intc: sifi
v
e_plic:
C
leanup the
i
rq_
r
equest
f
unction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
A
lista
i
r Fran
c
is
hw/intc:
s
i
f
ive_plic: Clean
u
p t
h
e rea
l
ize functi
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Alist
a
ir Fr
a
ncis
hw/
i
n
t
c: sifive
_
plic
:
Move the properties
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
A
list
a
ir Francis
hw/in
t
c: Remove the
I
bex
PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
A
l
i
stair
F
rancis
h
w
/
r
iscv: opentitan: Up
d
ate
t
o
the la
t
est build
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-21
Alistai
r
Francis
target/
r
iscv: Organise the CPU
p
roperties
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-21
Ali
s
tair Franc
i
s
target/r
i
scv:
R
em
o
ve some
u
nused macros
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-06
Alistair Francis
hw/riscv: shak
t
i_
c
: Mark as n
o
t us
e
r creatable
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-21
Alistair F
r
ancis
hw
/
riscv:
op
e
nti
t
an: Correct the USB Dev address
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Al
i
stair
F
ran
c
i
s
sifi
v
e_
u
: Connect the Si
F
ive P
W
M device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistair Francis
hw/timer:
A
dd SiFive
P
W
M
support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alis
t
air Francis
hw
/
intc: ibex_timer:
C
onve
r
t
the timer
t
o u
s
e RISC
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
A
l
ist
a
ir
F
rancis
hw/intc: sifive_plic: Convert the PLIC
t
o
us
e
RISC
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistair Francis
hw/i
n
tc: ibe
x
_plic: Co
n
vert the
P
L
IC to use R
I
SC-V
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
A
l
istair
F
ran
c
is
hw/intc:
s
ifiv
e
_cl
i
nt: Use RISC-V
C
PU G
P
IO lines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Ali
s
tair
F
r
a
nci
s
target/riscv: Expose interrupt pending bits
a
s GPIO
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alist
a
ir Francis
target/riscv: Updat
e
the ePMP CSR
a
ddre
s
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
Alist
a
ir Francis
hw/riscv/bo
o
t: C
h
e
c
k
th
e
error of fdt_pack()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
Al
i
stair Francis
hw/r
i
s
c
v: opentitan: Add the flash alia
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
Alistair
Francis
hw/r
i
scv:
opent
i
tan: A
d
d
t
he unimplement rv_
c
ore_ibex_peri
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
A
l
i
s
tair Fra
n
cis
char: ib
e
x
_
u
a
rt: Update the regist
e
r layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Alistair Fran
c
is
hw/riscv: Open
T
itan
:
Con
n
ect the
m
time
a
nd mtim
e
cmp
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Ali
s
tair Francis
h
w
/timer:
I
n
itial co
m
mit of
Ibex Time
r
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Alis
t
air Francis
hw/
c
har/
i
b
e
x
_
ua
r
t: M
a
ke
t
h
e register l
a
y
out pri
v
a
te
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Alistai
r
Francis
targ
e
t/
r
i
scv: Use ta
r
get_ulong for the Di
s
asConte
x
t
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-07
Alistair Fra
n
cis
target/ri
s
cv/pmp: Add asser
t
fo
r
ePMP oper
a
ti
o
n
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-07
Alistai
r
Fr
a
ncis
docs/syst
e
m: Move the RISC-V -bi
o
s informa
t
ion t
o
removed
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Franc
i
s
target/riscv: Fix the RV64H decode comment
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
i
stair Francis
target
/
riscv:
C
o
n
solidate
RV32/64 16-
b
it instr
u
ctions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
Francis
targe
t
/riscv: Consolid
a
te RV32/64 32-bit instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
t
arget/ri
s
cv: Re
m
ove a
n
unused
CASE_OP_3
2
_64
m
acro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fr
a
ncis
t
a
rget/riscv: Remove the
unus
e
d
HSTATUS_WPRI macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
targ
e
t/riscv:
R
emove the hardcoded SATP_MODE
m
acro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Franc
i
s
tar
g
et/risc
v
:
R
emove
t
he hardcoded M
S
T
ATUS_SD macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Ali
s
t
air Fra
n
cis
target/riscv: Rem
o
v
e
t
h
e hardcoded HGATP_MODE macr
o
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair F
r
anci
s
ta
r
ge
t
/riscv: R
e
m
ove t
h
e hardcoded SSTAT
U
S
_
S
D
macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Franci
s
targe
t
/
riscv: Remove the hardco
d
ed RVXLEN macr
o
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fran
c
is
targe
t
/riscv: Add ePMP support for
t
h
e Ibe
x
CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistai
r
Francis
target/riscv/
p
mp: Rem
o
ve outdated comm
e
nt
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
F
r
a
ncis
target/riscv: A
d
d the ePMP feature
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alist
a
ir Franci
s
target/riscv: Fi
x
the PMP is locked check whe
n
usin
g
TOR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
ista
i
r Franci
s
hw/ris
c
v: Enable VIRTIO_VGA for
RISC-V virt machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
hw/open
t
i
t
a
n: Update the interrupt layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fra
n
cis
M
AINTAINERS: Update
the RISC-V CP
U
Mai
n
tainers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair F
r
ancis
tar
g
et
/
riscv: Use RISCVException enum for CSR acc
e
ss
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alist
a
ir Francis
targe
t
/ri
s
cv:
U
se t
h
e
R
IS
C
VExceptio
n
enum for C
S
R op
e
ratio
n
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Ali
s
tair
Francis
targe
t
/
r
iscv
:
Fix 32-b
i
t HS mode access permiss
i
ons
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair F
r
ancis
target/riscv: Us
e
the RISCVE
x
ception enum for
C
SR predic
a
tes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
ista
i
r
F
rancis
target/
r
is
c
v:
C
on
v
ert th
e
R
I
SC
-
V exception
s
to
an enum
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-03-04
Al
i
stair Francis
MAINT
A
INE
R
S: Add a
SiFive m
a
chine sec
t
ion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-02-13
Alistair F
r
ancis
l
inux-user/signal: Decode waitid si_code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-01-16
Alist
a
ir
F
r
ancis
riscv: P
a
ss
R
ISCV
H
artArrayState by pointer
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
Alistair Francis
risc
v
/op
e
ntitan: U
p
date th
e
O
p
enT
i
ta
n
m
e
mor
y
layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
Alistai
r
Francis
hw/riscv
:
Use the CPU to determine if 32
-
bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
A
l
ista
i
r
F
ranci
s
ta
r
get/ri
s
cv: cpu:
S
et XLEN independently from target
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
Alistair Fr
a
ncis
t
a
rget/riscv
:
csr: Remo
v
e
compile t
i
m
e XLEN ch
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
Alistai
r
Francis
targe
t
/riscv: cp
u
_help
e
r: Re
m
ov
e
compile time X
L
EN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
Alistair
Francis
tar
g
et/riscv: cpu: Rem
o
ve
compile time XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
Alistair Fra
n
cis
target/riscv: S
p
ecify the XLEN for CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
Alista
i
r F
r
ancis
target/ris
c
v: Add a riscv_c
p
u_is_32
b
it() helper fu
n
ction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-12-18
Alistair Fran
c
i
s
targ
e
t/riscv: f
p
u_helper:
Match funct
i
on d
e
fs i
n
HELPER
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
Alistair Francis
hw/riscv: sifive_u: Remove c
o
mpil
e
tim
e
XLEN
checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2020-12-18
Al
i
stair Fr
a
ncis
hw/riscv: spike: Remove
c
ompile time
XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
A
l
istair Fran
c
is
hw/ri
s
c
v: virt: Remove compile time XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-12-18
Alista
i
r Franc
i
s
hw/riscv:
b
o
ot
:
Remove
c
o
m
pile time XLEN
c
hecks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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2020-12-18
Alistair
F
rancis
riscv: virt: Remove target macr
o
c
o
nditionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-12-18
Al
i
stair Franc
i
s
riscv:
spike: Remove target macro conditional
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2020-12-18
A
l
istair
F
r
ancis
t
arget/
r
isc
v
: Add a TYPE_R
I
SCV_CPU_BASE
C
PU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-12-18
Alistair Fr
a
n
cis
hw/
r
i
scv: Expan
d
the is 32-bit check to sup
p
o
rt mor
e
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-12-18
Al
i
stair Fr
a
ncis
intc/ibex_pl
i
c: Clear inter
r
upts that occur during
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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2020-11-17
Alistair Franci
s
r
egister: Rem
o
ve u
n
necessary NULL chec
k
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-11-14
Alistair Francis
intc/i
b
ex_
p
l
i
c: Ens
u
re we don't loose interrupts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-11-14
A
l
istair Francis
intc/ibex_plic:
F
i
x
some
typ
o
s in the comments
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-11-09
Ali
s
tair Fra
n
cis
hw/int
c
/ibex_p
l
ic:
Cle
a
r th
e
claim regis
t
e
r whe
n
read
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-11-09
Alistair Francis
t
a
r
get/riscv: Split the Hyper
v
isor execute load helpers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-11-09
A
listair Francis
targ
e
t/ri
s
cv: Remove the hyp load an
d
s
tore fu
n
ctions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-11-09
Ali
s
tair
F
rancis
t
arget/ris
c
v: Remove
t
h
e HS_TWO
_
STAGE flag
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-11-09
A
listai
r
Fr
a
n
cis
t
a
rget/ris
c
v: Set the virt
u
alised M
M
U mode when doing
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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