2021-06-07 | Bin Meng | hw/riscv: microchip_pfsoc: Support direct kernel boot Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: Use macros for BIOS image names Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | docs/system/riscv: sifive_u: Document '-dtb' usage Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | docs/system/riscv: Correct the indentation level of... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: Support the official PLIC DT bindings Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: Support the official CLINT DT bindings Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Bin Meng | hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_ar... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alistair Francis | target/riscv: Fix the RV64H decode comment Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...4b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Consolidate RV32/64 16-bit instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Consolidate RV32/64 32-bit instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove an unused CASE_OP_32_64 macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...0120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the unused HSTATUS_WPRI macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the hardcoded SATP_MODE macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the hardcoded MSTATUS_SD macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the hardcoded HGATP_MODE macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the hardcoded SSTATUS_SD macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Remove the hardcoded RVXLEN macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com |
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2021-05-11 | Emmanuel Blot | target/riscv: fix a typo with interrupt names Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Frank Chang | fpu/softfloat: set invalid excp flag for RISC-V muladd... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alexander Wagner | hw/riscv: Fix OT IBEX reset vector Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Emmanuel Blot | target/riscv: fix exception index on instruction access... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Frank Chang | target/riscv: fix vrgather macro index variable type bug Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alistair Francis | target/riscv: Add ePMP support for the Ibex CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv/pmp: Remove outdated comment Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...9a78fdba85280cab4dd27f.1618812899.git.alistair.francis@wdc.com |
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2021-05-11 | Hou Weiying | target/riscv: Add a config option for ePMP Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...35d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Hou Weiying | target/riscv: Implementation of enhanced PMP (ePMP) Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...4e7c98b168bdec5d297bb1.1618812899.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Hou Weiying | target/riscv: Add ePMP CSR access functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alistair Francis | target/riscv: Add the ePMP feature Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...c3ae009f5467e2b3960ce0.1618812899.git.alistair.francis@wdc.com |
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2021-05-11 | Hou Weiying | target/riscv: Define ePMP mseccfg Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alistair Francis | target/riscv: Fix the PMP is locked check when using TOR Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com |
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2021-05-11 | Vijai Kumar K | docs: Add documentation for shakti_c machine Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | LIU Zhiwei | target/riscv: Fixup saturate subtract function Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Jade Fink | riscv: don't look at SUM when accessing memory from... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Alistair Francis | hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | hw/opentitan: Update the interrupt layout Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...10da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | MAINTAINERS: Update the RISC-V CPU Maintainers Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Use RISCVException enum for CSR access Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Use the RISCVException enum for CSR operations Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Fix 32-bit HS mode access permissions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Use the RISCVException enum for CSR predicates Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com |
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2021-05-11 | Alistair Francis | target/riscv: Convert the RISC-V exceptions to an enum Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com |
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2021-05-11 | Vijai Kumar K | hw/riscv: Connect Shakti UART to Shakti platform Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Vijai Kumar K | hw/char: Add Shakti UART emulation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Vijai Kumar K | riscv: Add initial support for Shakti C machine Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Vijai Kumar K | target/riscv: Add Shakti C class CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Bin Meng | hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Dylan Jhong | target/riscv: Align the data type of reset vector address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Axel Heider | docs/system/generic-loader.rst: Fix style Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-05-11 | Atish Patra | target/riscv: Remove privilege v1.9 specific CSR related... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Prevent lost illegal instruction exceptions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Bin Meng | docs/system: riscv: Add documentation for 'microchip... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Bin Meng | hw/riscv: microchip_pfsoc: Map EMMC/SD mux register Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Bin Meng | hw/block: m25p80: Support fast read for SST flashes Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Add proper two-stage lookup exception... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Fix read and write accesses to vsip and... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Asherah Connor | hw/riscv: allow ramfb on virt Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Asherah Connor | hw/riscv: Add fw_cfg support to virt Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Use background registers also for MSTATUS_MPV Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Make VSTIP and VSEIP read-only in hip Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Adjust privilege level for HLV(X)/HSV... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Jim Shu | target/riscv: flush TLB pages if PMP permission has... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Jim Shu | target/riscv: add log of PMP permission checking Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Jim Shu | target/riscv: propagate PMP permission to TLB page Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Alexander Wagner | hw/char: disable ibex uart receive if the buffer is... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Frank Chang | target/riscv: fix vs() to return proper error code Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: virt: Map high mmio for PCIe Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: virt: Limit RAM size in a 32-bit system Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: Drop 'struct MemmapEntry' Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Alistair Francis | MAINTAINERS: Add a SiFive machine section Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...adf81ae194718f2f17c402.1612836645.git.alistair.francis@wdc.com |
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2021-03-04 | Laurent Vivier | goldfish_rtc: re-arm the alarm after migration Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | docs/system: riscv: Add documentation for sifive_u... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | docs/system: Add RISC-V documentation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | docs/system: Sort targets in alphabetical order Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: sifive_u: Add QSPI2 controller and connect... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: sifive_u: Add QSPI0 controller and connect... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/ssi: Add SiFive SPI controller support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/block: m25p80: Add various ISSI flash information Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/block: m25p80: Add ISSI SPI flash support Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Yifei Jiang | target-riscv: support QMP dump-guest-memory Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | roms/opensbi: Upgrade from v0.8 to v0.9 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/misc: sifive_u_otp: Use error_report() when block... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | target/riscv: Declare csr_ops[] with a known size Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Alistair Francis | riscv: Pass RISCVHartArrayState by pointer Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...69991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com |
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2021-01-16 | Bin Meng | target/riscv: Remove built-in GDB XML files for CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | target/riscv: Generate the GDB XML file for CSR registers... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | target/riscv: Add CSR name in the CSR function table Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | target/riscv: Make csr_ops[CSR_TABLE_SIZE] external Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Green Wan | hw/misc/sifive_u_otp: handling the fails of blk_pread... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Atish Patra | target/riscv/pmp: Raise exception if no PMP entry is... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Atish Patra | RISC-V: Place DTB at 3GB boundary instead of 4GB Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Sylvain Pelissier | gdb: riscv: Add target description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Xuzhou Cheng | hw/block: m25p80: Implement AAI-WP command support... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | hw/block: m25p80: Don't write to flash if write is... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | riscv/opentitan: Update the OpenTitan memory layout Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...a3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com |
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2020-12-18 | Alistair Francis | hw/riscv: Use the CPU to determine if 32-bit Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...7788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com |
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2020-12-18 | Alistair Francis | target/riscv: cpu: Set XLEN independently from target Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com |
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