target/riscv: Move the hfence instructions to the rvh decode
[qemu/ar7.git] / target / riscv / insn_trans / trans_rvh.inc.c
blob2c0359819d290bc4342ab1a219da43c72f5a640c
1 /*
2 * RISC-V translation routines for the RVXI Base Integer Instruction Set.
4 * Copyright (c) 2020 Western Digital
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
21 #ifndef CONFIG_USER_ONLY
22 if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
23 has_ext(ctx, RVH)) {
24 /* Hpervisor extensions exist */
26 * if (env->priv == PRV_M ||
27 * (env->priv == PRV_S &&
28 * !riscv_cpu_virt_enabled(env) &&
29 * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
31 gen_helper_tlb_flush(cpu_env);
32 return true;
33 /* } */
35 #endif
36 return false;
39 static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
41 #ifndef CONFIG_USER_ONLY
42 if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
43 has_ext(ctx, RVH)) {
44 /* Hpervisor extensions exist */
46 * if (env->priv == PRV_M ||
47 * (env->priv == PRV_S &&
48 * !riscv_cpu_virt_enabled(env) &&
49 * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
51 gen_helper_tlb_flush(cpu_env);
52 return true;
53 /* } */
55 #endif
56 return false;