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hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
[qemu/ar7.git]
/
hw
/
riscv
/
Kconfig
blob
ceb7c166a36dbc80e6a8be040f5752061131c9d9
1
config HTIF
2
bool
3
4
config HART
5
bool
6
7
config IBEX
8
bool
9
10
config SIFIVE
11
bool
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select MSI_NONBROKEN
13
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config SIFIVE_E
15
bool
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select HART
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select SIFIVE
18
select UNIMP
19
20
config SIFIVE_U
21
bool
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select CADENCE
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select HART
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select SIFIVE
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select UNIMP
26
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config SPIKE
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bool
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select HART
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select HTIF
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select SIFIVE
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config OPENTITAN
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bool
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select IBEX
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select HART
37
select UNIMP
38
39
config RISCV_VIRT
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bool
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imply PCI_DEVICES
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imply TEST_DEVICES
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select PCI
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select HART
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select SERIAL
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select GOLDFISH_RTC
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select VIRTIO_MMIO
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select PCI_EXPRESS_GENERIC_BRIDGE
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select PFLASH_CFI01
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select SIFIVE
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config MICROCHIP_PFSOC
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bool
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select HART
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select SIFIVE
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select UNIMP
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select MCHP_PFSOC_MMUART