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target/riscv: Support setting external interrupt by KVM
2022-01-21 Yifei Jiangtarget/riscv: Support setting external interrupt by KVM
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Support start kernel directly by KVM
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Implement kvm_arch_put_registers
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Implement kvm_arch_get_registers
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Implement function kvm_arch_init_vcpu
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangtarget/riscv: Add target/riscv/kvm.c to place the public...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Yifei Jiangupdate-linux-headers: Add asm-riscv/kvm.h
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Wilfred Mallawahw: timer: ibex_timer: update/add reg address
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Wilfred Mallawariscv: opentitan: fixup plic stride len
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-21 Wilfred Mallawahw: timer: ibex_timer: Fixup reading w/o register
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Implement the stval/mtval illegal instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Fixup setting GVA
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Set the opcode in DisasContext
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: actual functions to realize crs 128-bit...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: modification of the trans_csrxx for 128...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: helper functions to wrap calls to 128...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: adding high part of some csrs
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit M extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit arithmetic instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit shift instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit U-type instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit bitwise instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: accessors to registers upper part and...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: moving some insns close to similar insns
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: setup everything for rv64 to support...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: array for the 64 upper bits of 128-bit...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: separation of bitwise logic and arithmetic...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrottarget/riscv: additional macros to check instruction...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrotqemu/int128: addition of div/rem 128-bit operations
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrotexec/memop: Adding signed quad and octo defines
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frédéric Pétrotexec/memop: Adding signedness to quad definitions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Philipp Tomsichtarget/riscv: Fix position of 'experimental' comment
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frank Changtarget/riscv: rvv-1.0: Call the correct RVF/RVD check...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frank Changtarget/riscv: rvv-1.0: Call the correct RVF/RVD check...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Frank Changtarget/riscv: rvv-1.0: Call the correct RVF/RVD check...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Bin Mengroms/opensbi: Upgrade from v0.9 to v1.0
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/riscv: virt: Allow support for 32 cores
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/riscv: Use error_fatal for SoC realisation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Enable the Hypervisor extension by default
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Mark the Hypervisor extension as non...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup remaining functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup the read function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup the write function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Add a reset function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Jim Shuhw/dma: sifive_pdma: permit 4/8-byte access size of...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Jim Shuhw/dma: sifive_pdma: support high 32-bit access of...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Nikita Shubintarget/riscv/pmp: fix no pmp illegal intrs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Jessica Clarkehw/riscv: Use load address rather than entry point...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Vineet Guptatarget/riscv: Enable bitmanip Zb[abcs] instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Khem Rajriscv: Set 5.4 as minimum kernel version for riscv32
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: Add ELEN checks for widening...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: update opivv_vadc_check() comment
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: rename vmandnot.mm and vmornot...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add vector unit-stride mask...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add vsetivli instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point reciprocal estimate...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point reciprocal square...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Hsiangkai Wangtarget/riscv: gdb: support vector registers for rv64...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: trigger illegal instruction...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: implement vstart CSR
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing floating-point/integer...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: add "set round to odd" rounding mode...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point/integer...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point/integer type...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: introduce floating-point rounding mode...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point min/max instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove integer extract instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove widening saturating scaled...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width scaling shift instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point reduction...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width floating-point...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing fixed-point clip instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point slide instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: slide instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: mask-register logical instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point compare instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer comparison instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width saturating add...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening integer multiply-add...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing integer right shift...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer add-with-carry/subtract...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width bit shift instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width averaging add and...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer extension instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: whole register move instructions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point scalar move instructions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point move instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer scalar move instructions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: register gather instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: allow load element with sign...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: element index instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: iota instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: set-X-first mask bit instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: find-first-set mask bit instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: count population in mask instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point classify instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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