hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "fdc.h"
  27 #include "pci.h"
  28 #include "block.h"
  29 #include "sysemu.h"
  30 #include "audio/audio.h"
  31 #include "net.h"
  32 #include "smbus.h"
  33 #include "boards.h"
  34 #include "console.h"
  35 #include "fw_cfg.h"
  36
  37 #include "qemu-kvm.h"
  38
  39 /* output Bochs bios info messages */
  40 //#define DEBUG_BIOS
  41
  42 #define BIOS_FILENAME "bios.bin"
  43 #define VGABIOS_FILENAME "vgabios.bin"
  44 #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
  45 #define EXTBOOT_FILENAME "extboot.bin"
  46
  47 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  48
  49 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  50 #define ACPI_DATA_SIZE       0x10000
  51 #define BIOS_CFG_IOPORT 0x510
  52
  53 #define MAX_IDE_BUS 2
  54
  55 static fdctrl_t *floppy_controller;
  56 static RTCState *rtc_state;
  57 static PITState *pit;
  58 static IOAPICState *ioapic;
  59 static PCIDevice *i440fx_state;
  60
  61 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
  62 {
  63 }
  64
  65 /* MSDOS compatibility mode FPU exception support */
  66 static qemu_irq ferr_irq;
  67 /* XXX: add IGNNE support */
  68 void cpu_set_ferr(CPUX86State *s)
  69 {
  70     qemu_irq_raise(ferr_irq);
  71 }
  72
  73 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
  74 {
  75     qemu_irq_lower(ferr_irq);
  76 }
  77
  78 /* TSC handling */
  79 uint64_t cpu_get_tsc(CPUX86State *env)
  80 {
  81     /* Note: when using kqemu, it is more logical to return the host TSC
  82        because kqemu does not trap the RDTSC instruction for
  83        performance reasons */
  84 #ifdef USE_KQEMU
  85     if (env->kqemu_enabled) {
  86         return cpu_get_real_ticks();
  87     } else
  88 #endif
  89     {
  90         return cpu_get_ticks();
  91     }
  92 }
  93
  94 /* SMM support */
  95 void cpu_smm_update(CPUState *env)
  96 {
  97     if (i440fx_state && env == first_cpu)
  98         i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
  99 }
 100
 101
 102 /* IRQ handling */
 103 int cpu_get_pic_interrupt(CPUState *env)
 104 {
 105     int intno;
 106
 107     intno = apic_get_interrupt(env);
 108     if (intno >= 0) {
 109         /* set irq request if a PIC irq is still pending */
 110         /* XXX: improve that */
 111         pic_update_irq(isa_pic);
 112         return intno;
 113     }
 114     /* read the irq from the PIC */
 115     if (!apic_accept_pic_intr(env))
 116         return -1;
 117
 118     intno = pic_read_irq(isa_pic);
 119     return intno;
 120 }
 121
 122 static void pic_irq_request(void *opaque, int irq, int level)
 123 {
 124     CPUState *env = first_cpu;
 125
 126     if (env->apic_state) {
 127         while (env) {
 128             if (apic_accept_pic_intr(env))
 129                 apic_deliver_pic_intr(env, level);
 130             env = env->next_cpu;
 131         }
 132     } else {
 133         if (level)
 134             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 135         else
 136             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 137     }
 138 }
 139
 140 /* PC cmos mappings */
 141
 142 #define REG_EQUIPMENT_BYTE          0x14
 143
 144 static int cmos_get_fd_drive_type(int fd0)
 145 {
 146     int val;
 147
 148     switch (fd0) {
 149     case 0:
 150         /* 1.44 Mb 3"5 drive */
 151         val = 4;
 152         break;
 153     case 1:
 154         /* 2.88 Mb 3"5 drive */
 155         val = 5;
 156         break;
 157     case 2:
 158         /* 1.2 Mb 5"5 drive */
 159         val = 2;
 160         break;
 161     default:
 162         val = 0;
 163         break;
 164     }
 165     return val;
 166 }
 167
 168 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 169 {
 170     RTCState *s = rtc_state;
 171     int cylinders, heads, sectors;
 172     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 173     rtc_set_memory(s, type_ofs, 47);
 174     rtc_set_memory(s, info_ofs, cylinders);
 175     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 176     rtc_set_memory(s, info_ofs + 2, heads);
 177     rtc_set_memory(s, info_ofs + 3, 0xff);
 178     rtc_set_memory(s, info_ofs + 4, 0xff);
 179     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 180     rtc_set_memory(s, info_ofs + 6, cylinders);
 181     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 182     rtc_set_memory(s, info_ofs + 8, sectors);
 183 }
 184
 185 /* convert boot_device letter to something recognizable by the bios */
 186 static int boot_device2nibble(char boot_device)
 187 {
 188     switch(boot_device) {
 189     case 'a':
 190     case 'b':
 191         return 0x01; /* floppy boot */
 192     case 'c':
 193         return 0x02; /* hard drive boot */
 194     case 'd':
 195         return 0x03; /* CD-ROM boot */
 196     case 'n':
 197         return 0x04; /* Network boot */
 198     }
 199     return 0;
 200 }
 201
 202 /* copy/pasted from cmos_init, should be made a general function
 203  and used there as well */
 204 static int pc_boot_set(void *opaque, const char *boot_device)
 205 {
 206 #define PC_MAX_BOOT_DEVICES 3
 207     RTCState *s = (RTCState *)opaque;
 208     int nbds, bds[3] = { 0, };
 209     int i;
 210
 211     nbds = strlen(boot_device);
 212     if (nbds > PC_MAX_BOOT_DEVICES) {
 213         term_printf("Too many boot devices for PC\n");
 214         return(1);
 215     }
 216     for (i = 0; i < nbds; i++) {
 217         bds[i] = boot_device2nibble(boot_device[i]);
 218         if (bds[i] == 0) {
 219             term_printf("Invalid boot device for PC: '%c'\n",
 220                     boot_device[i]);
 221             return(1);
 222         }
 223     }
 224     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 225     rtc_set_memory(s, 0x38, (bds[2] << 4));
 226     return(0);
 227 }
 228
 229 /* hd_table must contain 4 block drivers */
 230 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 231                       const char *boot_device, BlockDriverState **hd_table)
 232 {
 233     RTCState *s = rtc_state;
 234     int nbds, bds[3] = { 0, };
 235     int val;
 236     int fd0, fd1, nb;
 237     int i;
 238
 239     /* various important CMOS locations needed by PC/Bochs bios */
 240
 241     /* memory size */
 242     val = 640; /* base memory in K */
 243     rtc_set_memory(s, 0x15, val);
 244     rtc_set_memory(s, 0x16, val >> 8);
 245
 246     val = (ram_size / 1024) - 1024;
 247     if (val > 65535)
 248         val = 65535;
 249     rtc_set_memory(s, 0x17, val);
 250     rtc_set_memory(s, 0x18, val >> 8);
 251     rtc_set_memory(s, 0x30, val);
 252     rtc_set_memory(s, 0x31, val >> 8);
 253
 254     if (above_4g_mem_size) {
 255         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 256         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 257         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 258     }
 259     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 260
 261     if (ram_size > (16 * 1024 * 1024))
 262         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 263     else
 264         val = 0;
 265     if (val > 65535)
 266         val = 65535;
 267     rtc_set_memory(s, 0x34, val);
 268     rtc_set_memory(s, 0x35, val >> 8);
 269
 270     /* set the number of CPU */
 271     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 272
 273     /* set boot devices, and disable floppy signature check if requested */
 274 #define PC_MAX_BOOT_DEVICES 3
 275     nbds = strlen(boot_device);
 276     if (nbds > PC_MAX_BOOT_DEVICES) {
 277         fprintf(stderr, "Too many boot devices for PC\n");
 278         exit(1);
 279     }
 280     for (i = 0; i < nbds; i++) {
 281         bds[i] = boot_device2nibble(boot_device[i]);
 282         if (bds[i] == 0) {
 283             fprintf(stderr, "Invalid boot device for PC: '%c'\n",
 284                     boot_device[i]);
 285             exit(1);
 286         }
 287     }
 288     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 289     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
 290
 291     /* floppy type */
 292
 293     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 294     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 295
 296     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 297     rtc_set_memory(s, 0x10, val);
 298
 299     val = 0;
 300     nb = 0;
 301     if (fd0 < 3)
 302         nb++;
 303     if (fd1 < 3)
 304         nb++;
 305     switch (nb) {
 306     case 0:
 307         break;
 308     case 1:
 309         val |= 0x01; /* 1 drive, ready for boot */
 310         break;
 311     case 2:
 312         val |= 0x41; /* 2 drives, ready for boot */
 313         break;
 314     }
 315     val |= 0x02; /* FPU is there */
 316     val |= 0x04; /* PS/2 mouse installed */
 317     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 318
 319     /* hard drives */
 320
 321     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 322     if (hd_table[0])
 323         cmos_init_hd(0x19, 0x1b, hd_table[0]);
 324     if (hd_table[1])
 325         cmos_init_hd(0x1a, 0x24, hd_table[1]);
 326
 327     val = 0;
 328     for (i = 0; i < 4; i++) {
 329         if (hd_table[i]) {
 330             int cylinders, heads, sectors, translation;
 331             /* NOTE: bdrv_get_geometry_hint() returns the physical
 332                 geometry.  It is always such that: 1 <= sects <= 63, 1
 333                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 334                 geometry can be different if a translation is done. */
 335             translation = bdrv_get_translation_hint(hd_table[i]);
 336             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 337                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 338                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 339                     /* No translation. */
 340                     translation = 0;
 341                 } else {
 342                     /* LBA translation. */
 343                     translation = 1;
 344                 }
 345             } else {
 346                 translation--;
 347             }
 348             val |= translation << (i * 2);
 349         }
 350     }
 351     rtc_set_memory(s, 0x39, val);
 352 }
 353
 354 void ioport_set_a20(int enable)
 355 {
 356     /* XXX: send to all CPUs ? */
 357     cpu_x86_set_a20(first_cpu, enable);
 358 }
 359
 360 int ioport_get_a20(void)
 361 {
 362     return ((first_cpu->a20_mask >> 20) & 1);
 363 }
 364
 365 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 366 {
 367     ioport_set_a20((val >> 1) & 1);
 368     /* XXX: bit 0 is fast reset */
 369 }
 370
 371 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 372 {
 373     return ioport_get_a20() << 1;
 374 }
 375
 376 /***********************************************************/
 377 /* Bochs BIOS debug ports */
 378
 379 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 380 {
 381     static const char shutdown_str[8] = "Shutdown";
 382     static int shutdown_index = 0;
 383
 384     switch(addr) {
 385         /* Bochs BIOS messages */
 386     case 0x400:
 387     case 0x401:
 388         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 389         exit(1);
 390     case 0x402:
 391     case 0x403:
 392 #ifdef DEBUG_BIOS
 393         fprintf(stderr, "%c", val);
 394 #endif
 395         break;
 396     case 0x8900:
 397         /* same as Bochs power off */
 398         if (val == shutdown_str[shutdown_index]) {
 399             shutdown_index++;
 400             if (shutdown_index == 8) {
 401                 shutdown_index = 0;
 402                 qemu_system_shutdown_request();
 403             }
 404         } else {
 405             shutdown_index = 0;
 406         }
 407         break;
 408
 409         /* LGPL'ed VGA BIOS messages */
 410     case 0x501:
 411     case 0x502:
 412         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 413         exit(1);
 414     case 0x500:
 415     case 0x503:
 416 #ifdef DEBUG_BIOS
 417         fprintf(stderr, "%c", val);
 418 #endif
 419         break;
 420     }
 421 }
 422
 423 static void bochs_bios_init(void)
 424 {
 425     void *fw_cfg;
 426
 427     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 428     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 429     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 430     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 431     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 432
 433     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 434     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 435     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 436     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 437
 438     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 439     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 440     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 441 }
 442
 443 /* Generate an initial boot sector which sets state and jump to
 444    a specified vector */
 445 static void generate_bootsect(uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
 446 {
 447     uint8_t bootsect[512], *p;
 448     int i;
 449     int hda = extboot_drive;
 450
 451     if (hda == -1)
 452       hda = drive_get_index(IF_IDE, 0, 0);
 453     if (hda == -1) {
 454         fprintf(stderr, "A disk image must be given for 'hda' when booting "
 455                 "a Linux kernel\n(if you really don't want it, use /dev/zero)\n");
 456         exit(1);
 457     }
 458
 459     memset(bootsect, 0, sizeof(bootsect));
 460
 461     /* Copy the MSDOS partition table if possible */
 462     bdrv_read(drives_table[hda].bdrv, 0, bootsect, 1);
 463
 464     /* Make sure we have a partition signature */
 465     bootsect[510] = 0x55;
 466     bootsect[511] = 0xaa;
 467
 468     /* Actual code */
 469     p = bootsect;
 470     *p++ = 0xfa;                /* CLI */
 471     *p++ = 0xfc;                /* CLD */
 472
 473     for (i = 0; i < 6; i++) {
 474         if (i == 1)             /* Skip CS */
 475             continue;
 476
 477         *p++ = 0xb8;            /* MOV AX,imm16 */
 478         *p++ = segs[i];
 479         *p++ = segs[i] >> 8;
 480         *p++ = 0x8e;            /* MOV <seg>,AX */
 481         *p++ = 0xc0 + (i << 3);
 482     }
 483
 484     for (i = 0; i < 8; i++) {
 485         *p++ = 0x66;            /* 32-bit operand size */
 486         *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
 487         *p++ = gpr[i];
 488         *p++ = gpr[i] >> 8;
 489         *p++ = gpr[i] >> 16;
 490         *p++ = gpr[i] >> 24;
 491     }
 492
 493     *p++ = 0xea;                /* JMP FAR */
 494     *p++ = ip;                  /* IP */
 495     *p++ = ip >> 8;
 496     *p++ = segs[1];             /* CS */
 497     *p++ = segs[1] >> 8;
 498
 499     bdrv_set_boot_sector(drives_table[hda].bdrv, bootsect, sizeof(bootsect));
 500 }
 501
 502 static long get_file_size(FILE *f)
 503 {
 504     long where, size;
 505
 506     /* XXX: on Unix systems, using fstat() probably makes more sense */
 507
 508     where = ftell(f);
 509     fseek(f, 0, SEEK_END);
 510     size = ftell(f);
 511     fseek(f, where, SEEK_SET);
 512
 513     return size;
 514 }
 515
 516 static void load_linux(const char *kernel_filename,
 517                        const char *initrd_filename,
 518                        const char *kernel_cmdline)
 519 {
 520     uint16_t protocol;
 521     uint32_t gpr[8];
 522     uint16_t seg[6];
 523     uint16_t real_seg;
 524     int setup_size, kernel_size, initrd_size, cmdline_size;
 525     uint32_t initrd_max;
 526     uint8_t header[1024];
 527     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr;
 528     FILE *f, *fi;
 529
 530     /* Align to 16 bytes as a paranoia measure */
 531     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 532
 533     /* load the kernel header */
 534     f = fopen(kernel_filename, "rb");
 535     if (!f || !(kernel_size = get_file_size(f)) ||
 536         fread(header, 1, 1024, f) != 1024) {
 537         fprintf(stderr, "qemu: could not load kernel '%s'\n",
 538                 kernel_filename);
 539         exit(1);
 540     }
 541
 542     /* kernel protocol version */
 543 #if 0
 544     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 545 #endif
 546     if (ldl_p(header+0x202) == 0x53726448)
 547         protocol = lduw_p(header+0x206);
 548     else
 549         protocol = 0;
 550
 551     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 552         /* Low kernel */
 553         real_addr    = 0x90000;
 554         cmdline_addr = 0x9a000 - cmdline_size;
 555         prot_addr    = 0x10000;
 556     } else if (protocol < 0x202) {
 557         /* High but ancient kernel */
 558         real_addr    = 0x90000;
 559         cmdline_addr = 0x9a000 - cmdline_size;
 560         prot_addr    = 0x100000;
 561     } else {
 562         /* High and recent kernel */
 563         real_addr    = 0x10000;
 564         cmdline_addr = 0x20000;
 565         prot_addr    = 0x100000;
 566     }
 567
 568 #if 0
 569     fprintf(stderr,
 570             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 571             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 572             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 573             real_addr,
 574             cmdline_addr,
 575             prot_addr);
 576 #endif
 577
 578     /* highest address for loading the initrd */
 579     if (protocol >= 0x203)
 580         initrd_max = ldl_p(header+0x22c);
 581     else
 582         initrd_max = 0x37ffffff;
 583
 584     if (initrd_max >= ram_size-ACPI_DATA_SIZE)
 585         initrd_max = ram_size-ACPI_DATA_SIZE-1;
 586
 587     /* kernel command line */
 588     pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
 589
 590     if (protocol >= 0x202) {
 591         stl_p(header+0x228, cmdline_addr);
 592     } else {
 593         stw_p(header+0x20, 0xA33F);
 594         stw_p(header+0x22, cmdline_addr-real_addr);
 595     }
 596
 597     /* loader type */
 598     /* High nybble = B reserved for Qemu; low nybble is revision number.
 599        If this code is substantially changed, you may want to consider
 600        incrementing the revision. */
 601     if (protocol >= 0x200)
 602         header[0x210] = 0xB0;
 603
 604     /* heap */
 605     if (protocol >= 0x201) {
 606         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 607         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 608     }
 609
 610     /* load initrd */
 611     if (initrd_filename) {
 612         if (protocol < 0x200) {
 613             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 614             exit(1);
 615         }
 616
 617         fi = fopen(initrd_filename, "rb");
 618         if (!fi) {
 619             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 620                     initrd_filename);
 621             exit(1);
 622         }
 623
 624         initrd_size = get_file_size(fi);
 625         initrd_addr = (initrd_max-initrd_size) & ~4095;
 626
 627         fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx
 628                 "\n", initrd_size, initrd_addr);
 629
 630         if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
 631             fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
 632                     initrd_filename);
 633             exit(1);
 634         }
 635         fclose(fi);
 636
 637         stl_p(header+0x218, initrd_addr);
 638         stl_p(header+0x21c, initrd_size);
 639     }
 640
 641     /* store the finalized header and load the rest of the kernel */
 642     cpu_physical_memory_write(real_addr, header, 1024);
 643
 644     setup_size = header[0x1f1];
 645     if (setup_size == 0)
 646         setup_size = 4;
 647
 648     setup_size = (setup_size+1)*512;
 649     kernel_size -= setup_size;  /* Size of protected-mode code */
 650
 651     if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) ||
 652         !fread_targphys_ok(prot_addr, kernel_size, f)) {
 653         fprintf(stderr, "qemu: read error on kernel '%s'\n",
 654                 kernel_filename);
 655         exit(1);
 656     }
 657     fclose(f);
 658
 659     /* generate bootsector to set up the initial register state */
 660     real_seg = real_addr >> 4;
 661     seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
 662     seg[1] = real_seg+0x20;     /* CS */
 663     memset(gpr, 0, sizeof gpr);
 664     gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */
 665
 666     generate_bootsect(gpr, seg, 0);
 667 }
 668
 669 static void main_cpu_reset(void *opaque)
 670 {
 671     CPUState *env = opaque;
 672     cpu_reset(env);
 673 }
 674
 675 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 676 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 677 static const int ide_irq[2] = { 14, 15 };
 678
 679 #define NE2000_NB_MAX 6
 680
 681 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
 682 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 683
 684 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 685 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 686
 687 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 688 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 689
 690 #ifdef HAS_AUDIO
 691 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 692 {
 693     struct soundhw *c;
 694     int audio_enabled = 0;
 695
 696     for (c = soundhw; !audio_enabled && c->name; ++c) {
 697         audio_enabled = c->enabled;
 698     }
 699
 700     if (audio_enabled) {
 701         AudioState *s;
 702
 703         s = AUD_init ();
 704         if (s) {
 705             for (c = soundhw; c->name; ++c) {
 706                 if (c->enabled) {
 707                     if (c->isa) {
 708                         c->init.init_isa (s, pic);
 709                     }
 710                     else {
 711                         if (pci_bus) {
 712                             c->init.init_pci (pci_bus, s);
 713                         }
 714                     }
 715                 }
 716             }
 717         }
 718     }
 719 }
 720 #endif
 721
 722 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 723 {
 724     static int nb_ne2k = 0;
 725
 726     if (nb_ne2k == NE2000_NB_MAX)
 727         return;
 728     isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
 729     nb_ne2k++;
 730 }
 731
 732 typedef struct rom_reset_data {
 733     uint8_t *data;
 734     target_phys_addr_t addr;
 735     unsigned size;
 736 } RomResetData;
 737
 738 static void option_rom_reset(void *_rrd)
 739 {
 740     RomResetData *rrd = _rrd;
 741
 742     cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
 743 }
 744
 745 static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
 746 {
 747     RomResetData *rrd = qemu_malloc(sizeof *rrd);
 748
 749     rrd->data = qemu_malloc(size);
 750     cpu_physical_memory_read(addr, rrd->data, size);
 751     rrd->addr = addr;
 752     rrd->size = size;
 753     qemu_register_reset(option_rom_reset, rrd);
 754 }
 755
 756 static int load_option_rom(const char *filename, int offset, int type)
 757 {
 758     ram_addr_t option_rom_offset;
 759     int size, ret;
 760
 761     size = get_image_size(filename);
 762     if (size < 0) {
 763         fprintf(stderr, "Could not load option rom '%s'\n", filename);
 764         exit(1);
 765     }
 766     if (size > (0x10000 - offset))
 767         goto option_rom_error;
 768     option_rom_offset = qemu_ram_alloc(size);
 769     ret = load_image(filename, phys_ram_base + option_rom_offset);
 770     if (ret != size) {
 771     option_rom_error:
 772         fprintf(stderr, "Too many option ROMS\n");
 773         exit(1);
 774     }
 775     size = (size + 4095) & ~4095;
 776     cpu_register_physical_memory(0xd0000 + offset,
 777                                  size, option_rom_offset | type);
 778     option_rom_setup_reset(0xd0000 + offset, size);
 779
 780     return size;
 781 }
 782
 783 CPUState *pc_new_cpu(int cpu, const char *cpu_model, int pci_enabled)
 784 {
 785         CPUState *env = cpu_init(cpu_model);
 786         if (!env) {
 787             fprintf(stderr, "Unable to find x86 CPU definition\n");
 788             exit(1);
 789         }
 790         if (cpu != 0)
 791             env->halted = 1;
 792         if (smp_cpus > 1) {
 793             /* XXX: enable it in all cases */
 794             env->cpuid_features |= CPUID_APIC;
 795         }
 796         qemu_register_reset(main_cpu_reset, env);
 797         if (pci_enabled) {
 798             apic_init(env);
 799         }
 800         return env;
 801 }
 802
 803 /* PC hardware initialisation */
 804 static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
 805                      const char *boot_device, DisplayState *ds,
 806                      const char *kernel_filename, const char *kernel_cmdline,
 807                      const char *initrd_filename,
 808                      int pci_enabled, const char *cpu_model)
 809 {
 810     char buf[1024];
 811     int ret, linux_boot, i;
 812     ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;
 813     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 814     int bios_size, isa_bios_size, vga_bios_size, opt_rom_offset;
 815     PCIBus *pci_bus;
 816     int piix3_devfn = -1;
 817     CPUState *env;
 818     NICInfo *nd;
 819     qemu_irq *cpu_irq;
 820     qemu_irq *i8259;
 821     int index;
 822     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 823     BlockDriverState *fd[MAX_FD];
 824
 825     if (ram_size >= 0xe0000000 ) {
 826         above_4g_mem_size = ram_size - 0xe0000000;
 827         below_4g_mem_size = 0xe0000000;
 828     } else {
 829         below_4g_mem_size = ram_size;
 830     }
 831
 832     linux_boot = (kernel_filename != NULL);
 833
 834     /* init CPUs */
 835     if (cpu_model == NULL) {
 836 #ifdef TARGET_X86_64
 837         cpu_model = "qemu64";
 838 #else
 839         cpu_model = "qemu32";
 840 #endif
 841     }
 842
 843     for(i = 0; i < smp_cpus; i++) {
 844         env = pc_new_cpu(i, cpu_model, pci_enabled);
 845     }
 846
 847     vmport_init();
 848
 849     /* allocate RAM */
 850     ram_addr = qemu_ram_alloc(0xa0000);
 851     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 852
 853     /* Allocate, even though we won't register, so we don't break the
 854      * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
 855      * and some bios areas, which will be registered later
 856      */
 857     ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
 858     ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
 859     cpu_register_physical_memory(0x100000,
 860                  below_4g_mem_size - 0x100000,
 861                  ram_addr);
 862
 863     /* above 4giga memory allocation */
 864     if (above_4g_mem_size > 0) {
 865         if (hpagesize) {
 866             if (ram_addr & (hpagesize-1)) {
 867                 unsigned long aligned_addr;
 868                 aligned_addr = (ram_addr + hpagesize - 1) & ~(hpagesize-1);
 869                 qemu_ram_alloc(aligned_addr - ram_addr);
 870                 ram_addr = aligned_addr;
 871             }
 872         }
 873         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 874         cpu_register_physical_memory(0x100000000ULL,
 875                                      above_4g_mem_size,
 876                                      ram_addr);
 877     }
 878
 879     /* allocate VGA RAM */
 880     vga_ram_addr = qemu_ram_alloc(vga_ram_size);
 881
 882     /* BIOS load */
 883     if (bios_name == NULL)
 884         bios_name = BIOS_FILENAME;
 885     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 886     bios_size = get_image_size(buf);
 887     if (bios_size <= 0 ||
 888         (bios_size % 65536) != 0) {
 889         goto bios_error;
 890     }
 891     bios_offset = qemu_ram_alloc(bios_size);
 892     ret = load_image(buf, phys_ram_base + bios_offset);
 893     if (ret != bios_size) {
 894     bios_error:
 895         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
 896         exit(1);
 897     }
 898
 899     /* VGA BIOS load */
 900     if (cirrus_vga_enabled) {
 901         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME);
 902     } else {
 903         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 904     }
 905     vga_bios_size = get_image_size(buf);
 906     if (vga_bios_size <= 0 || vga_bios_size > 65536)
 907         goto vga_bios_error;
 908     vga_bios_offset = qemu_ram_alloc(65536);
 909
 910     ret = load_image(buf, phys_ram_base + vga_bios_offset);
 911     if (ret != vga_bios_size) {
 912     vga_bios_error:
 913         fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf);
 914         exit(1);
 915     }
 916
 917     /* setup basic memory access */
 918     cpu_register_physical_memory(0xc0000, 0x10000,
 919                                  vga_bios_offset | IO_MEM_ROM);
 920
 921     /* map the last 128KB of the BIOS in ISA space */
 922     isa_bios_size = bios_size;
 923     if (isa_bios_size > (128 * 1024))
 924         isa_bios_size = 128 * 1024;
 925     cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
 926                                  IO_MEM_UNASSIGNED);
 927     /* kvm tpr optimization needs the bios accessible for write, at least to qemu itself */
 928     cpu_register_physical_memory(0x100000 - isa_bios_size,
 929                                  isa_bios_size,
 930                                  (bios_offset + bios_size - isa_bios_size) /* | IO_MEM_ROM */);
 931
 932     /* XXX: for DDIM support, "ROM space" should be writable during
 933        initialization, and (optionally) marked readonly by the BIOS
 934        before INT 19h.  See the PNPBIOS specification, appendix B.
 935        DDIM support is mandatory for proper PCI expansion ROM support. */
 936     opt_rom_offset = 0;
 937     for (i = 0; i < nb_option_roms; i++)
 938         opt_rom_offset += load_option_rom(option_rom[i], opt_rom_offset,
 939                                           IO_MEM_ROM);
 940
 941     if (extboot_drive != -1) {
 942         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, EXTBOOT_FILENAME);
 943         opt_rom_offset += load_option_rom(buf, opt_rom_offset, IO_MEM_RAM);
 944     }
 945
 946     /* map all the bios at the top of memory */
 947     cpu_register_physical_memory((uint32_t)(-bios_size),
 948                                  bios_size, bios_offset | IO_MEM_ROM);
 949
 950     bochs_bios_init();
 951
 952     if (linux_boot)
 953         load_linux(kernel_filename, initrd_filename, kernel_cmdline);
 954
 955     cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
 956     i8259 = i8259_init(cpu_irq[0]);
 957     ferr_irq = i8259[13];
 958
 959     if (pci_enabled) {
 960         pci_bus = i440fx_init(&i440fx_state, i8259);
 961         piix3_devfn = piix3_init(pci_bus, -1);
 962     } else {
 963         pci_bus = NULL;
 964     }
 965
 966     /* init basic PC hardware */
 967     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 968
 969     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
 970
 971     if (cirrus_vga_enabled) {
 972         if (pci_enabled) {
 973             pci_cirrus_vga_init(pci_bus,
 974                                 ds, phys_ram_base + vga_ram_addr,
 975                                 vga_ram_addr, vga_ram_size);
 976         } else {
 977             isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr,
 978                                 vga_ram_addr, vga_ram_size);
 979         }
 980     } else if (vmsvga_enabled) {
 981         if (pci_enabled)
 982             pci_vmsvga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
 983                             vga_ram_addr, vga_ram_size);
 984         else
 985             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 986     } else {
 987         if (pci_enabled) {
 988             pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
 989                          vga_ram_addr, vga_ram_size, 0, 0);
 990         } else {
 991             isa_vga_init(ds, phys_ram_base + vga_ram_addr,
 992                          vga_ram_addr, vga_ram_size);
 993         }
 994     }
 995
 996     rtc_state = rtc_init(0x70, i8259[8]);
 997
 998     qemu_register_boot_set(pc_boot_set, rtc_state);
 999
1000     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1001     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1002
1003     if (pci_enabled) {
1004         ioapic = ioapic_init();
1005     }
1006 #ifdef USE_KVM_PIT
1007     if (kvm_enabled() && qemu_kvm_pit_in_kernel())
1008         pit = kvm_pit_init(0x40, i8259[0]);
1009     else
1010 #endif
1011         pit = pit_init(0x40, i8259[0]);
1012     pcspk_init(pit);
1013     if (pci_enabled) {
1014         pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
1015     }
1016
1017     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1018         if (serial_hds[i]) {
1019             serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
1020                         serial_hds[i]);
1021         }
1022     }
1023
1024     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1025         if (parallel_hds[i]) {
1026             parallel_init(parallel_io[i], i8259[parallel_irq[i]],
1027                           parallel_hds[i]);
1028         }
1029     }
1030
1031     for(i = 0; i < nb_nics; i++) {
1032         nd = &nd_table[i];
1033         if (!nd->model) {
1034             if (pci_enabled) {
1035                 nd->model = "rtl8139";
1036             } else {
1037                 nd->model = "ne2k_isa";
1038             }
1039         }
1040         if (strcmp(nd->model, "ne2k_isa") == 0) {
1041             pc_init_ne2k_isa(nd, i8259);
1042         } else if (pci_enabled) {
1043             if (strcmp(nd->model, "?") == 0)
1044                 fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
1045             if (!pci_nic_init(pci_bus, nd, -1))
1046                 exit(1);
1047         } else if (strcmp(nd->model, "?") == 0) {
1048             fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
1049             exit(1);
1050         } else {
1051             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
1052             exit(1);
1053         }
1054     }
1055
1056     qemu_system_hot_add_init(cpu_model);
1057
1058     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1059         fprintf(stderr, "qemu: too many IDE bus\n");
1060         exit(1);
1061     }
1062
1063     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1064         index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1065         if (index != -1)
1066             hd[i] = drives_table[index].bdrv;
1067         else
1068             hd[i] = NULL;
1069     }
1070
1071     if (pci_enabled) {
1072         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
1073     } else {
1074         for(i = 0; i < MAX_IDE_BUS; i++) {
1075             isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
1076                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1077         }
1078     }
1079
1080     i8042_init(i8259[1], i8259[12], 0x60);
1081     DMA_init(0);
1082 #ifdef HAS_AUDIO
1083     audio_init(pci_enabled ? pci_bus : NULL, i8259);
1084 #endif
1085
1086     for(i = 0; i < MAX_FD; i++) {
1087         index = drive_get_index(IF_FLOPPY, 0, i);
1088         if (index != -1)
1089             fd[i] = drives_table[index].bdrv;
1090         else
1091             fd[i] = NULL;
1092     }
1093     floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1094
1095     cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1096
1097     if (pci_enabled && usb_enabled) {
1098         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1099     }
1100
1101     if (pci_enabled && acpi_enabled) {
1102         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1103         i2c_bus *smbus;
1104
1105         /* TODO: Populate SPD eeprom data.  */
1106         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1107         for (i = 0; i < 8; i++) {
1108             smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
1109         }
1110     }
1111
1112     if (i440fx_state) {
1113         i440fx_init_memory_mappings(i440fx_state);
1114     }
1115
1116     if (pci_enabled) {
1117         int max_bus;
1118         int bus, unit;
1119         void *scsi;
1120
1121         max_bus = drive_get_max_bus(IF_SCSI);
1122
1123         for (bus = 0; bus <= max_bus; bus++) {
1124             scsi = lsi_scsi_init(pci_bus, -1);
1125             for (unit = 0; unit < LSI_MAX_DEVS; unit++) {
1126                 index = drive_get_index(IF_SCSI, bus, unit);
1127                 if (index == -1)
1128                     continue;
1129                 lsi_scsi_attach(scsi, drives_table[index].bdrv, unit);
1130             }
1131         }
1132     }
1133
1134     /* Add virtio block devices */
1135     if (pci_enabled) {
1136         int index;
1137         int unit_id = 0;
1138
1139         while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
1140             virtio_blk_init(pci_bus, 0x1AF4, 0x1001,
1141                             drives_table[index].bdrv);
1142             unit_id++;
1143         }
1144     }
1145
1146     if (extboot_drive != -1) {
1147         DriveInfo *info = &drives_table[extboot_drive];
1148         int cyls, heads, secs;
1149
1150         if (info->type != IF_IDE && info->type != IF_VIRTIO) {
1151             bdrv_guess_geometry(info->bdrv, &cyls, &heads, &secs);
1152             bdrv_set_geometry_hint(info->bdrv, cyls, heads, secs);
1153         }
1154
1155         extboot_init(info->bdrv, 1);
1156     }
1157
1158     if (pci_enabled)
1159         virtio_balloon_init(pci_bus);
1160 }
1161
1162 static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
1163                         const char *boot_device, DisplayState *ds,
1164                         const char *kernel_filename,
1165                         const char *kernel_cmdline,
1166                         const char *initrd_filename,
1167                         const char *cpu_model)
1168 {
1169     pc_init1(ram_size, vga_ram_size, boot_device, ds,
1170              kernel_filename, kernel_cmdline,
1171              initrd_filename, 1, cpu_model);
1172 }
1173
1174 static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
1175                         const char *boot_device, DisplayState *ds,
1176                         const char *kernel_filename,
1177                         const char *kernel_cmdline,
1178                         const char *initrd_filename,
1179                         const char *cpu_model)
1180 {
1181     pc_init1(ram_size, vga_ram_size, boot_device, ds,
1182              kernel_filename, kernel_cmdline,
1183              initrd_filename, 0, cpu_model);
1184 }
1185
1186 QEMUMachine pc_machine = {
1187     .name = "pc",
1188     .desc = "Standard PC",
1189     .init = pc_init_pci,
1190     .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1191     .max_cpus = 255,
1192 };
1193
1194 QEMUMachine isapc_machine = {
1195     .name = "isapc",
1196     .desc = "ISA-only PC",
1197     .init = pc_init_isa,
1198     .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1199     .max_cpus = 1,
1200 };