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2023-10-09	Juzhe-Zhong	RISC-V Regression tests: Fix FAIL of pr97832* for RVV	commit \| commitdiff \| tree
2023-10-09	Juzhe-Zhong	RISC-V Regression test: Fix FAIL of slp-12a.c	commit \| commitdiff \| tree
2023-10-09	Juzhe-Zhong	RISC-V Regression test: Fix FAIL of slp-reduc-4.c for RVV	commit \| commitdiff \| tree
2023-10-09	Juzhe-Zhong	RISC-V Regression test: Adapt SLP tests like ARM SVE	commit \| commitdiff \| tree
2023-10-09	Juzhe-Zhong	RISC-V: Support movmisalign of RVV VLA modes	commit \| commitdiff \| tree
2023-10-09	Pan Li	RISC-V: Refine bswap16 auto vectorization code gen Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-10-09	Juzhe-Zhong	RISC-V Regression test: Fix FAIL of pr45752.c for RVV	commit \| commitdiff \| tree
2023-10-09	Juzhe-Zhong	RISC-V Regression test: Fix FAIL of fast-math-slp-38...	commit \| commitdiff \| tree
2023-10-08	Yanzhang Wang	RISC-V: add static-pie support	commit \| commitdiff \| tree
2023-10-08	Juzhe-Zhong	TEST: Fix XPASS of TSVC testsuites for RVV	commit \| commitdiff \| tree
2023-10-08	Juzhe-Zhong	RISC-V: Enable more tests of "vect" for RVV	commit \| commitdiff \| tree
2023-10-07	Pan Li	RISC-V: Add more run test for FP rounding autovec Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-10-07	Pan Li	RISC-V: Bugfix for legitimize address PR/111634 Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-10-06	Pan Li	RISC-V: Update comments for FP rounding related autovec Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-10-05	Juzhe-Zhong	RISC-V: Remove @ of vec_series	commit \| commitdiff \| tree
2023-09-28	Pan Li	RISC-V: Support {U}INT64 to FP16 auto-vectorization Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-27	Pan Li	RISC-V: Support FP roundeven auto-vectorization Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-27	Juzhe-Zhong	DSE: Fix ICE when the mode with access_size don't exist...	commit \| commitdiff \| tree
2023-09-27	Juzhe-Zhong	ifcvt: Fix comments	commit \| commitdiff \| tree
2023-09-27	Pan Li	RISC-V: Support FP trunc auto-vectorization Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-26	Juzhe-Zhong	MATCH: Optimize COND_ADD reduction pattern	commit \| commitdiff \| tree
2023-09-26	Juzhe-Zhong	MATCH: Optimize COND_ADD_LEN reduction pattern	commit \| commitdiff \| tree
2023-09-26	Pan Li	RISC-V: Support FP round auto-vectorization Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-26	Pan Li	RISC-V: Support FP rint auto-vectorization Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-26	Pan Li	RISC-V: Support FP nearbyint auto-vectorization Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-26	Pan Li	RISC-V: Rename rounding const fp function for refactor Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-25	Juzhe-Zhong	RISC-V: Fix AVL/VL bug of VSETVL PASS[PR111548]	commit \| commitdiff \| tree
2023-09-24	Pan Li	RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-24	Juzhe-Zhong	RISC-V: Support full coverage VLS combine support	commit \| commitdiff \| tree
2023-09-23	Juzhe-Zhong	RISC-V: Add VLS unary combine patterns	commit \| commitdiff \| tree
2023-09-23	Pan Li	RISC-V: Suport FP floor auto-vectorization Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-23	Pan Li	RISC-V: Remove FP run test for ceil. Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-22	Pan Li	RISC-V: Refine the code gen for ceil auto vectorization. Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-22	Pan Li	RISC-V: Move ceil test cases to unop folder Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-22	Pan Li	RISC-V: Rename the test macro for math autovec test Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-22	Pan Li	RISC-V: Remove arch and abi option for run test case. Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-22	Pan Li	RISC-V: Leverage __builtin_xx instead of math.h for... Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-22	Pan Li	RISC-V: Support ceil and ceilf auto-vectorization Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-21	Juzhe-Zhong	RISC-V: Add VLS integer ABS support	commit \| commitdiff \| tree
2023-09-21	Juzhe-Zhong	RISC-V: Add more VLS unary tests	commit \| commitdiff \| tree
2023-09-21	Juzhe-Zhong	RISC-V: Support VLS mult high	commit \| commitdiff \| tree
2023-09-20	Yanzhang Wang	RISC-V: Support simplifying x/(-1) to neg for vector.	commit \| commitdiff \| tree
2023-09-18	Pan Li	RISC-V: Support VLS mode for vec_set Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-18	Pan Li	RISC-V: Bugfix for scalar move with merged operand Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-18	Juzhe-Zhong	RISC-V: Fix VSETVL PASS fusion bug	commit \| commitdiff \| tree
2023-09-18	Juzhe-Zhong	RISC-V: Support VLS modes vec_init auto-vectorization	commit \| commitdiff \| tree
2023-09-18	Juzhe-Zhong	RISC-V: Remove autovec-vls.md file and clean up VLS...	commit \| commitdiff \| tree
2023-09-18	Juzhe-Zhong	RISC-V: Support VLS modes reduction[PR111153]	commit \| commitdiff \| tree
2023-09-16	Juzhe-Zhong	RISC-V: Expand VLS mode to scalar mode move[PR111391]	commit \| commitdiff \| tree
2023-09-16	Pan Li	RISC-V: Support FP SGNJX autovec for VLS mode Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-15	Juzhe-Zhong	test: Block SLP check of slp-35.c for vect_strided5	commit \| commitdiff \| tree
2023-09-15	Juzhe-Zhong	test: Block SLP check of slp-34.c for vect_strided5	commit \| commitdiff \| tree
2023-09-15	Juzhe-Zhong	test: Block vect_strided5 for slp-34-big-array.c SLP...	commit \| commitdiff \| tree
2023-09-15	Juzhe-Zhong	test: Block slp-16.c check for target support vect_strided6	commit \| commitdiff \| tree
2023-09-15	Juzhe-Zhong	test: Isolate slp-1.c check of target supports vect_strided5	commit \| commitdiff \| tree
2023-09-15	Juzhe-Zhong	test: Remove XPASS for RISCV	commit \| commitdiff \| tree
2023-09-14	Juzhe-Zhong	RISC-V: Support VLS modes mask operations	commit \| commitdiff \| tree
2023-09-14	Juzhe-Zhong	RISC-V: Fix ICE in get_avl_or_vl_reg	commit \| commitdiff \| tree
2023-09-14	Juzhe-Zhong	RISC-V: Format VSETVL PASS code	commit \| commitdiff \| tree
2023-09-13	Juzhe-Zhong	RISC-V: Support VLS modes VEC_EXTRACT auto-vectorization	commit \| commitdiff \| tree
2023-09-13	Pan Li	RISC-V: Bugfix PR111362 for incorrect frm emit Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-12	Pan Li	RISC-V: Remove unused structure in cost model Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-12	Juzhe-Zhong	RISC-V: Support Dynamic LMUL Cost model	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Enable RVV scalable vectorization by default...	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Remove redundant functions	commit \| commitdiff \| tree
2023-09-10	Juzhe-Zhong	RISC-V: Expand fixed-vlmax/vls vector permutation in...	commit \| commitdiff \| tree
2023-09-10	Juzhe-Zhong	RISC-V: Avoid unnecessary slideup in compress pattern...	commit \| commitdiff \| tree
2023-09-10	Juzhe-Zhong	RISC-V: Fix dump FILE of VSETVL PASS[PR111311]	commit \| commitdiff \| tree
2023-09-09	Juzhe-Zhong	RISC-V: Fix VLS floating-point operations predicate	commit \| commitdiff \| tree
2023-09-08	Juzhe-Zhong	RISC-V: Suppress bogus warning for VLS types	commit \| commitdiff \| tree
2023-09-08	Juzhe-Zhong	RISC-V: Fix incorrect nregs calculation for VLS modes	commit \| commitdiff \| tree
2023-09-07	Juzhe-Zhong	RISC-V: Remove incorrect earliest vsetvl post optimization...	commit \| commitdiff \| tree
2023-09-06	Juzhe-Zhong	RISC-V: Fix incorrect mode tieable which cause ICE...	commit \| commitdiff \| tree
2023-09-06	Juzhe-Zhong	RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295]	commit \| commitdiff \| tree
2023-09-06	Juzhe-Zhong	RISC-V: Remove unreasonable TARGET_64BIT for VLS modes...	commit \| commitdiff \| tree
2023-09-06	Pan Li	RISC-V: Fix incorrect folder for VRGATHERI16 test case Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-05	Pan Li	RISC-V: Support FP SGNJ autovec for VLS mode Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-04	Pan Li	RISC-V: Support FP16 for RVV VRGATHEREI16 intrinsic Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-03	Pan Li	RISC-V: Support FP MAX/MIN autovec for VLS mode Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-09-01	Juzhe-Zhong	RISC-V: Enable VECT_COMPARE_COSTS by default	commit \| commitdiff \| tree
2023-09-01	Juzhe-Zhong	RISC-V: Add dynamic LMUL compile option	commit \| commitdiff \| tree
2023-09-01	Pan Li	RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS... Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-08-31	Pan Li	RISC-V: Support rounding mode for VFNMADD/VFNMACC autovec Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-08-31	Pan Li	RISC-V: Support rounding mode for VFNMSAC/VFNMSUB autovec Signed-off-by: Pan Li <pan2.li@intel.com> Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-08-31	Pan Li	RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-08-31	Pan Li	RISC-V: Support rounding mode for VFMADD/VFMACC autovec Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-08-31	Juzhe-Zhong	RISC-V: Add Vector cost model framework for RVV	commit \| commitdiff \| tree
2023-08-30	Juzhe-Zhong	test: Add xfail into slp-reduc-7.c for RVV VLA vectorization	commit \| commitdiff \| tree
2023-08-30	Juzhe-Zhong	test: Adapt slp-26.c check for RVV	commit \| commitdiff \| tree
2023-08-30	Juzhe-Zhong	test: Fix XPASS of RVV	commit \| commitdiff \| tree
2023-08-30	Juzhe-Zhong	test: Add xfail for riscv_vector	commit \| commitdiff \| tree
2023-08-30	Juzhe-Zhong	RISC-V: Make sure we get VL REG operand for VLMAX vsetvl	commit \| commitdiff \| tree
2023-08-30	Juzhe-Zhong	RISC-V: Enable movmisalign for VLS modes	commit \| commitdiff \| tree
2023-08-29	Pan Li	RISC-V: Fix one ICE for vect test vect-multitypes-5 Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-08-28	Juzhe-Zhong	RISC-V: Fix uninitialized probability for GIMPLE IR...	commit \| commitdiff \| tree
2023-08-28	Juzhe-Zhong	RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL...	commit \| commitdiff \| tree
2023-08-26	Juzhe-Zhong	RISC-V: Support LEN_FOLD_EXTRACT_LAST auto-vectorization	commit \| commitdiff \| tree
2023-08-25	Juzhe-Zhong	RISC-V: Add early continue for ENTRY and EXIT block	commit \| commitdiff \| tree
2023-08-24	Juzhe-Zhong	RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS...	commit \| commitdiff \| tree
2023-08-24	Juzhe-Zhong	gimple_fold: Support COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNM...	commit \| commitdiff \| tree
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