RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS mode
commited60ffd814c86a225a4586da649f6e76718490db
authorPan Li <pan2.li@intel.com>
Fri, 1 Sep 2023 03:11:57 +0000 (1 11:11 +0800)
committerPan Li <pan2.li@intel.com>
Fri, 1 Sep 2023 08:31:57 +0000 (1 16:31 +0800)
treee492210b62e7b63d4104c1605f60efba4204f785
parent3d86e7f4a8aef1b864a51660825597eafe9059b1
RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS mode

This patch would like to allow the VLS mode autovec for the
floating-point binary operation ADD/SUB/MUL/DIV.

Given below code example:

test (float *out, float *in1, float *in2)
{
  for (int i = 0; i < 128; i++)
    out[i] = in1[i] + in2[i];
}

Before this patch:
test:
  csrr a4,vlenb
  slli a4,a4,1
  li   a5,128
  bleu a5,a4,.L38
  mv   a5,a4
.L38:
  vsetvli  zero,a5,e32,m8,ta,ma
  vle32.v  v16,0(a1)
  vsetvli  a4,zero,e32,m8,ta,ma
  vmv.v.i  v8,0
  vsetvli  zero,a5,e32,m8,tu,ma
  vle32.v  v24,0(a2)
  vfadd.vv v8,v24,v16
  vse32.v  v8,0(a0)
  ret

After this patch:
test:
  li       a5,128
  vsetvli  zero,a5,e32,m1,ta,ma
  vle32.v  v1,0(a2)
  vle32.v  v2,0(a1)
  vfadd.vv v1,v1,v2
  vse32.v  v1,0(a0)
  ret

Please note this patch also fix the execution failure of below
vect test cases.

* vect-alias-check-10.c
* vect-alias-check-11.c
* vect-alias-check-12.c
* vect-alias-check-14.c

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

* config/riscv/autovec-vls.md (<optab><mode>3): New pattern for
vls floating-point autovec.
* config/riscv/vector-iterators.md: New iterator for
floating-point V and VLS.
* config/riscv/vector.md: Add VLS to floating-point binop.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/def.h:
* gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c: New test.
16 files changed:
gcc/config/riscv/autovec-vls.md
gcc/config/riscv/vector-iterators.md
gcc/config/riscv/vector.md
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c [new file with mode: 0644]