| commit | deb844c67f1e2b116518f9742a6acbe6f19ea28f | |
| author | Pan Li <pan2.li@intel.com> | |
| Sun, 24 Sep 2023 03:36:11 +0000 (24 11:36 +0800) | ||
| committer | Pan Li <pan2.li@intel.com> | |
| Sun, 24 Sep 2023 09:09:35 +0000 (24 17:09 +0800) | ||
| tree | 99a6e040c02fa6d166102fa29c7d6f9cea4135d6 | treesnapshot (tar.gz zip) |
| parent | c23ce23e9ce162c49bca8900c8a20079b49501c9 | commitdiff |
RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
When broadcast the reperated element, we take the mask_int_mode
by mistake. This patch would like to fix it by leveraging the machine
mode of the element.
The below test case in RV32 will be fixed.
* gcc/testsuite/gfortran.dg/overload_5.f90
PR target/111546
gcc/ChangeLog:
* config/riscv/riscv-v.cc
(expand_vector_init_merge_repeating_sequence): Bugfix
Signed-off-by: Pan Li <pan2.li@intel.com>
When broadcast the reperated element, we take the mask_int_mode
by mistake. This patch would like to fix it by leveraging the machine
mode of the element.
The below test case in RV32 will be fixed.
* gcc/testsuite/gfortran.dg/overload_5.f90
PR target/111546
gcc/ChangeLog:
* config/riscv/riscv-v.cc
(expand_vector_init_merge_repeating_sequence): Bugfix
Signed-off-by: Pan Li <pan2.li@intel.com>
| gcc/config/riscv/riscv-v.cc | diffblobblamehistory |