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RISC-V: Document optimization parameter riscv-strcmp-inline-limit
2023-12-04 Christoph MüllnerRISC-V: Document optimization parameter riscv-strcmp...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-11-07 Christoph MüllnerRISC-V: Use stdint-gcc.h in xtheadmemidx-helpers.h
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-11-07 Christoph MüllnerRISC-V: Add ABI requirement for XTheadFMemIdx tests
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-10-31 Christoph Müllnerriscv: thead: Add support for the XTheadFMemIdx ISA...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-10-31 Christoph Müllnerriscv: thead: Add support for the XTheadMemIdx ISA...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-10-16 Christoph MüllnerRISC-V: NFC: Move scalar block move expansion code...
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2023-10-12 Christoph MüllnerRISC-V: Make xtheadcondmov-indirect tests robust against...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-10-10 Christoph MüllnerMAINTAINERS: Add myself to write after approval
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-09-12 Christoph Müllnerriscv: Add support for str(n)cmp inline expansion
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-09-12 Christoph Müllnerriscv: Add support for strlen inline expansion
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-09-08 Christoph Müllnerriscv: xtheadbb: Fix extendqi<SUPERQI> insn
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-09-08 Christoph Müllnerriscv: thead: Fix mode attribute for extension patterns
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-09-08 Christoph Müllnerriscv: bitmanip: Remove duplicate zero_extendhi<GPR...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-09-06 Christoph Müllnerriscv: xtheadbb: Fix xtheadbb-li-rotr test for rv32
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-09-05 Christoph Müllnerriscv: Synthesize all 11-bit-rotate constants with...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-09-05 Christoph Müllnerriscv: xtheadbb: Enable constant synthesis with th...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-09-05 Christoph Müllnerriscv: xtheadcondmov: Don't run tests with -Oz
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-17 Christoph Müllnerriscv: Fix warning in riscv_regno_ok_for_index_p
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-12 Christoph Müllnerriscv: thead: Fix failing XTheadCondMov tests (indirect...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-12 Christoph Müllnerriscv: thead: Factor out XThead*-specific peepholes
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-12 Christoph Müllnerriscv: Prepare backend for index registers
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-12 Christoph Müllnerriscv: Move address classification info types to riscv...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-12 Christoph Müllnerriscv: Define Xmode macro
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-12 Christoph Müllnerriscv: Simplify output of MEM addresses
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-12 Christoph Müllnerriscv: thead: Adjust constraints of th_addsl INSN
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-12 Christoph Müllnerriscv: xtheadmempair: Fix doc for th_mempair_order_operands()
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-12 Christoph Müllnerriscv: xtheadmempair: Fix CFA reg notes
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-12 Christoph Müllnerriscv: xtheadbb: Add sign/zero extension support for...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-07-03 Christoph MüllnerRISC-V: Add support for vector crypto extensions
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-03-27 Christoph Müllnertarget/109296 - riscv: Add missing mode specifiers...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-03-15 Christoph Müllnerriscv: thead: Add support for the XTheadMemPair ISA...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-03-15 Christoph Müllnerriscv: thead: Add support for the XTheadFmv ISA extension
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-03-15 Christoph Müllnerriscv: thead: Add support for the XTheadMac ISA extension
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-03-15 Christoph Müllnerriscv: thead: Add support for the XTheadCondMov ISA...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-03-15 Christoph Müllnerriscv: thead: Add support for the XTheadBb ISA extension
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-03-15 Christoph Müllnerriscv: thead: Add support for the XTheadBs ISA extension
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-03-15 Christoph Müllnerriscv: thead: Add support for the XTheadBa ISA extension
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-03-15 Christoph Müllnerriscv: riscv-cores.def: Add T-Head XuanTie C906
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-03-15 Christoph Müllnerriscv: Add basic XThead* vendor extension support
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2022-12-27 Christoph Müllnerriscv: Restructure callee-saved register save/restore...
...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2022-12-27 Christoph Müllnerriscv: attr: Synchronize comments with code
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2022-11-16 Christoph Müllnerdoc: invoke: pru/riscv: Fix option list formatting
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2022-11-02 Christoph MüllnerRISC-V: Add Zawrs ISA extension support
 ...off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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