RISC-V: Eliminate extension after for *w instructions

RISC-V: Eliminate extension after for *w instructions

This patch tries to prevent generating unnecessary sign extension
after *w instructions like "addiw" or "divw".

The main idea of it is to add SUBREG_PROMOTED fields during expanding.

I have tested on SPEC2017 there is no regression.
Only gcc.dg/pr30957-1.c test failed.
To solve that I did some changes in loop-iv.cc, but not sure that it is
suitable.

gcc/ChangeLog:
	* config/riscv/bitmanip.md (rotrdi3, rotrsi3, rotlsi3): New expanders.
	(rotrsi3_sext): Expose generator.
	(rotlsi3 pattern): Hide generator.
	* config/riscv/riscv-protos.h (riscv_emit_binary): New function
	declaration.
	* config/riscv/riscv.cc (riscv_emit_binary): Removed static
	* config/riscv/riscv.md (addsi3, subsi3, negsi2): Hide generator.
	(mulsi3, <optab>si3): Likewise.
	(addsi3, subsi3, negsi2, mulsi3, <optab>si3): New expanders.
	(addv<mode>4, subv<mode>4, mulv<mode>4): Use riscv_emit_binary.
	(<u>mulsidi3): Likewise.
	(addsi3_extended, subsi3_extended, negsi2_extended): Expose generator.
	(mulsi3_extended, <optab>si3_extended): Likewise.
	(splitter for shadd feeding divison): Update RTL pattern to account
	for changes in how 32 bit ops are expanded for TARGET_64BIT.
	* loop-iv.cc (get_biv_step_1): Process src of extension when it PLUS.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/shift-and-2.c: New tests.
	* gcc.target/riscv/shift-shift-2.c: Adjust expected output.
	* gcc.target/riscv/sign-extend.c: New test.
	* gcc.target/riscv/zbb-rol-ror-03.c: Adjust expected output.

Co-authored-by: Jeff Law  <jlaw@ventanamicro.com>