gcc/config/riscv/riscv-protos.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2023 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_PROTOS_H
  23 #define GCC_RISCV_PROTOS_H
  24
  25 #include "memmodel.h"
  26
  27 /* Symbol types we understand.  The order of this list must match that of
  28    the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST.  */
  29 enum riscv_symbol_type {
  30   SYMBOL_ABSOLUTE,
  31   SYMBOL_PCREL,
  32   SYMBOL_GOT_DISP,
  33   SYMBOL_TLS,
  34   SYMBOL_TLS_LE,
  35   SYMBOL_TLS_IE,
  36   SYMBOL_TLS_GD
  37 };
  38 #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
  39
  40 /* Routines implemented in riscv.cc.  */
  41 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
  42 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
  43 extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
  44 extern int riscv_address_insns (rtx, machine_mode, bool);
  45 extern int riscv_const_insns (rtx);
  46 extern int riscv_split_const_insns (rtx);
  47 extern int riscv_load_store_insns (rtx, rtx_insn *);
  48 extern rtx riscv_emit_move (rtx, rtx);
  49 extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *);
  50 extern bool riscv_split_symbol_type (enum riscv_symbol_type);
  51 extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
  52 extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode);
  53 extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
  54 extern rtx riscv_subword (rtx, bool);
  55 extern bool riscv_split_64bit_move_p (rtx, rtx);
  56 extern void riscv_split_doubleword_move (rtx, rtx);
  57 extern const char *riscv_output_move (rtx, rtx);
  58 extern const char *riscv_output_return ();
  59
  60 #ifdef RTX_CODE
  61 extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
  62 extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
  63 extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
  64 extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y);
  65 #endif
  66 extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx);
  67 extern rtx riscv_legitimize_call_address (rtx);
  68 extern void riscv_set_return_address (rtx, rtx);
  69 extern bool riscv_expand_block_move (rtx, rtx, rtx);
  70 extern rtx riscv_return_addr (int, rtx);
  71 extern poly_int64 riscv_initial_elimination_offset (int, int);
  72 extern void riscv_expand_prologue (void);
  73 extern void riscv_expand_epilogue (int);
  74 extern bool riscv_epilogue_uses (unsigned int);
  75 extern bool riscv_can_use_return_insn (void);
  76 extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
  77 extern bool riscv_expand_block_move (rtx, rtx, rtx);
  78 extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
  79 extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
  80 extern bool riscv_gpr_save_operation_p (rtx);
  81 extern void riscv_reinit (void);
  82 extern poly_uint64 riscv_regmode_natural_size (machine_mode);
  83 extern bool riscv_v_ext_vector_mode_p (machine_mode);
  84 extern bool riscv_v_ext_tuple_mode_p (machine_mode);
  85 extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
  86 extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
  87 extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *);
  88 extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel);
  89
  90 /* Routines implemented in riscv-c.cc.  */
  91 void riscv_cpu_cpp_builtins (cpp_reader *);
  92 void riscv_register_pragmas (void);
  93
  94 /* Routines implemented in riscv-builtins.cc.  */
  95 extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
  96 extern bool riscv_gimple_fold_builtin (gimple_stmt_iterator *);
  97 extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int);
  98 extern tree riscv_builtin_decl (unsigned int, bool);
  99 extern void riscv_init_builtins (void);
 100
 101 /* Routines implemented in riscv-common.cc.  */
 102 extern std::string riscv_arch_str (bool version_p = true);
 103 extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t);
 104
 105 extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
 106
 107 rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt);
 108 rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt);
 109
 110 /* Information about one CPU we know about.  */
 111 struct riscv_cpu_info {
 112   /* This CPU's canonical name.  */
 113   const char *name;
 114
 115   /* Default arch for this CPU, could be NULL if no default arch.  */
 116   const char *arch;
 117
 118   /* Which automaton to use for tuning.  */
 119   const char *tune;
 120 };
 121
 122 extern const riscv_cpu_info *riscv_find_cpu (const char *);
 123
 124 /* Routines implemented in riscv-selftests.cc.  */
 125 #if CHECKING_P
 126 namespace selftest {
 127 void riscv_run_selftests (void);
 128 } // namespace selftest
 129 #endif
 130
 131 namespace riscv_vector {
 132 #define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
 133 #define RVV_VUNDEF(MODE)                                                       \
 134   gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)),        \
 135                   UNSPEC_VUNDEF)
 136 enum insn_type
 137 {
 138   RVV_MISC_OP = 1,
 139   RVV_UNOP = 2,
 140   RVV_BINOP = 3,
 141   RVV_BINOP_MU = RVV_BINOP + 2,
 142   RVV_MERGE_OP = 4,
 143   RVV_CMP_OP = 4,
 144   RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand.  */
 145   RVV_UNOP_MU = RVV_UNOP + 2,     /* Likewise.  */
 146   RVV_TERNOP = 5,
 147   RVV_WIDEN_TERNOP = 4,
 148   RVV_SCALAR_MOV_OP = 4, /* +1 for VUNDEF according to vector.md.  */
 149 };
 150 enum vlmul_type
 151 {
 152   LMUL_1 = 0,
 153   LMUL_2 = 1,
 154   LMUL_4 = 2,
 155   LMUL_8 = 3,
 156   LMUL_RESERVED = 4,
 157   LMUL_F8 = 5,
 158   LMUL_F4 = 6,
 159   LMUL_F2 = 7,
 160   NUM_LMUL = 8
 161 };
 162
 163 enum avl_type
 164 {
 165   NONVLMAX,
 166   VLMAX,
 167 };
 168 /* Routines implemented in riscv-vector-builtins.cc.  */
 169 void init_builtins (void);
 170 const char *mangle_builtin_type (const_tree);
 171 #ifdef GCC_TARGET_H
 172 bool verify_type_context (location_t, type_context_kind, const_tree, bool);
 173 bool expand_vec_perm_const (machine_mode, machine_mode, rtx, rtx, rtx,
 174                             const vec_perm_indices &);
 175 #endif
 176 void handle_pragma_vector (void);
 177 tree builtin_decl (unsigned, bool);
 178 gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *);
 179 rtx expand_builtin (unsigned int, tree, rtx);
 180 bool check_builtin_call (location_t, vec<location_t>, unsigned int,
 181                            tree, unsigned int, tree *);
 182 bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 183 bool legitimize_move (rtx, rtx);
 184 void emit_vlmax_vsetvl (machine_mode, rtx);
 185 void emit_hard_vlmax_vsetvl (machine_mode, rtx);
 186 void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
 187 void emit_vlmax_ternary_insn (unsigned, int, rtx *, rtx = 0);
 188 void emit_nonvlmax_insn (unsigned, int, rtx *, rtx);
 189 void emit_vlmax_merge_insn (unsigned, int, rtx *);
 190 void emit_vlmax_cmp_insn (unsigned, rtx *);
 191 void emit_vlmax_cmp_mu_insn (unsigned, rtx *);
 192 void emit_vlmax_masked_mu_insn (unsigned, int, rtx *);
 193 enum vlmul_type get_vlmul (machine_mode);
 194 unsigned int get_ratio (machine_mode);
 195 unsigned int get_nf (machine_mode);
 196 machine_mode get_subpart_mode (machine_mode);
 197 int get_ta (rtx);
 198 int get_ma (rtx);
 199 int get_avl_type (rtx);
 200 unsigned int calculate_ratio (unsigned int, enum vlmul_type);
 201 enum tail_policy
 202 {
 203   TAIL_UNDISTURBED = 0,
 204   TAIL_AGNOSTIC = 1,
 205   TAIL_ANY = 2,
 206 };
 207
 208 enum mask_policy
 209 {
 210   MASK_UNDISTURBED = 0,
 211   MASK_AGNOSTIC = 1,
 212   MASK_ANY = 2,
 213 };
 214 enum tail_policy get_prefer_tail_policy ();
 215 enum mask_policy get_prefer_mask_policy ();
 216 rtx get_avl_type_rtx (enum avl_type);
 217 opt_machine_mode get_vector_mode (scalar_mode, poly_uint64);
 218 opt_machine_mode get_tuple_mode (machine_mode, unsigned int);
 219 bool simm5_p (rtx);
 220 bool neg_simm5_p (rtx);
 221 #ifdef RTX_CODE
 222 bool has_vi_variant_p (rtx_code, rtx);
 223 void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
 224 bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
 225 #endif
 226 bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode,
 227                           bool, void (*)(rtx *, rtx));
 228 rtx gen_scalar_move_mask (machine_mode);
 229
 230 /* RVV vector register sizes.
 231    TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to
 232    support other values in the future.  */
 233 enum vlen_enum
 234 {
 235   RVV_32 = 32,
 236   RVV_64 = 64,
 237   RVV_65536 = 65536
 238 };
 239 bool slide1_sew64_helper (int, machine_mode, machine_mode,
 240                           machine_mode, rtx *);
 241 rtx gen_avl_for_scalar_move (rtx);
 242 void expand_tuple_move (rtx *);
 243 machine_mode preferred_simd_mode (scalar_mode);
 244 opt_machine_mode get_mask_mode (machine_mode);
 245 void expand_vec_series (rtx, rtx, rtx);
 246 void expand_vec_init (rtx, rtx);
 247 void expand_vcond (rtx *);
 248 void expand_vec_perm (rtx, rtx, rtx, rtx);
 249 /* Rounding mode bitfield for fixed point VXRM.  */
 250 enum vxrm_field_enum
 251 {
 252   VXRM_RNU,
 253   VXRM_RNE,
 254   VXRM_RDN,
 255   VXRM_ROD
 256 };
 257 /* Rounding mode bitfield for floating point FRM.  */
 258 enum frm_field_enum
 259 {
 260   FRM_RNE = 0b000,
 261   FRM_RTZ = 0b001,
 262   FRM_RDN = 0b010,
 263   FRM_RUP = 0b011,
 264   FRM_RMM = 0b100,
 265   FRM_DYN = 0b111
 266 };
 267
 268 opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
 269                                          poly_uint64);
 270 unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
 271 }
 272
 273 /* We classify builtin types into two classes:
 274    1. General builtin class which is defined in riscv_builtins.
 275    2. Vector builtin class which is a special builtin architecture
 276       that implement intrinsic short into "pragma".  */
 277 enum riscv_builtin_class
 278 {
 279   RISCV_BUILTIN_GENERAL,
 280   RISCV_BUILTIN_VECTOR
 281 };
 282
 283 const unsigned int RISCV_BUILTIN_SHIFT = 1;
 284
 285 /* Mask that selects the riscv_builtin_class part of a function code.  */
 286 const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1;
 287
 288 /* Routines implemented in thead.cc.  */
 289 extern bool th_mempair_operands_p (rtx[4], bool, machine_mode);
 290 extern void th_mempair_order_operands (rtx[4], bool, machine_mode);
 291 extern void th_mempair_prepare_save_restore_operands (rtx[4], bool,
 292                                                       machine_mode,
 293                                                       int, HOST_WIDE_INT,
 294                                                       int, HOST_WIDE_INT);
 295 extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode);
 296 #ifdef RTX_CODE
 297 extern const char*
 298 th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
 299 #endif
 300
 301 extern bool riscv_use_divmod_expander (void);
 302 #endif /* ! GCC_RISCV_PROTOS_H */